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150 msps wideband digital down-converter (ddc) AD6636 rev. 0 in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . features 4/6 independe n t wideband pr ocessing chann e ls processes 6 wi deband carrier s (umts, c d ma 2000) 4 single-en ded o r 2 lvds paral l el input po rts (16 line ar bit pl us 3-bit exponent) running at 150 m hz supports 300 msps input usi n g external int e rface logic 3 16-bit par a lle l output ports operating up to 200 mhz real or complex input ports quadrature correction and dc correction for complex inputs supports output rate up to 34 msps per channel rms/peak pow e r monitoring of input ports programmable attenuator control for external gain ranging 3 programmable coefficient fir filters per channel 2 decimating h a lf-band filters per channel 6 programmable digita l a g c l oops with 96 d b range synchronous serial i/o operation (spi?-, sport-compatible) supports 8-bit or 16-bit microport modes 3.3 v i/o, 1.8 v cmos core user-configura ble built-in self -test (bist) cap a bility jtag bo undar y scan applic ati o ns multicarrier, m u ltimode digit a l receivers gsm, edge, ph s, umts, wc d m a, cdm a 200 0, td-s cdma micro and pico cell syst ems, so ftware radios b r o a dband dat a applicatio ns instrumentation and test eq ui pment wireless local l oop in-building wir e less te lephony func ti on a l bl ock di a g r a m in pu t ma tr ix cmos real ports a, b, c,d cmos complex ports (ai, aq) (bi, bq) lvds ports ab, cd peak/ rms meas. i,q corr. sync [3:0] ______ reset dat a rout er mat r ix dat a rout ing agc pa r a llel por t s 16-bit microport interface sport/spi interface jtag pll clock multiplier fir2 hb2 m = byp, 2 cic5 m = 1-32 nco fir1 hb1 m = byp, 2 crcf m = 1-16 mrcf drcf m = 1-16 lhb l = byp, 2 fir2 hb2 m = byp, 2 cic5 m = 1-32 nco fir1 hb1 m = byp, 2 crcf m = 1-16 mrcf drcf m = 1-16 lhb l = byp, 2 fir2 hb2 m = byp, 2 cic5 m = 1-32 nco fir1 hb1 m = byp, 2 crcf m = 1-16 mrcf drcf m = 1-16 lhb l = byp, 2 fir2 hb2 m = byp, 2 cic5 m = 1-32 nco fir1 hb1 m = byp, 2 crcf m = 1-16 mrcf drcf m = 1-16 lhb l = byp, 2 fir2 hb2 m = byp, 2 cic5 m = 1-32 nco fir1 hb1 m = byp, 2 crcf m = 1-16 mrcf drcf m = 1-16 lhb l = byp, 2 fir2 hb2 m = byp, 2 cic5 m = 1-32 nco fir1 hb1 m = byp, 2 crcf m = 1-16 mrcf drcf m = 1-16 lhb l = byp, 2 pa pb pc adc b/aq clkb expb [2:0] adc a/ai clka expa [2:0] adc d/cq clkd expd [2:0] adc c/ci clkc expc [2:0] m = decimation l = interpolation are available only in 6-channel part 04998-0-001 note: channels rendered as fi g u r e 1 .
AD6636 rev. 0 | page 2 of 72 table of contents product description......................................................................... 3 product highlights ....................................................................... 4 specifications..................................................................................... 5 electrical characteristics ............................................................. 5 general timing characteristics ................................................. 6 microport timing characteristics ............................................. 7 serial port timing characteristics ............................................. 8 explanation of test levels for specifications............................ 8 absolute maximum ratings............................................................ 9 thermal characteristics .............................................................. 9 esd caution.................................................................................. 9 pin configuration and function descriptions........................... 10 pin listing for power, ground, data and address buses ...... 12 timing diagrams............................................................................ 13 theory of operation ...................................................................... 19 adc input port .......................................................................... 19 pll clock multiplier ................................................................. 20 adc gain control ..................................................................... 21 adc input port monitor function.......................................... 22 quadrature i/q correction block............................................ 24 input crossbar matrix ............................................................... 26 numerically controlled oscillator (nco) ............................. 26 fifth-order cic filter ............................................................... 28 fir half-band block.................................................................. 29 intermediate data router ......................................................... 32 mono-rate ram coefficient filter (mrcf) ......................... 32 decimating ram coefficient filter (drcf) ........................ 33 channel ram coefficient filter (crcf) ............................... 35 interpolating half-band filter.................................................. 36 output data router ................................................................... 37 automatic gain control............................................................ 39 parallel port output ................................................................... 43 user-configurable built-in self-test (bist) .......................... 47 chip synchronization ................................................................ 47 serial port control ..................................................................... 48 microport .................................................................................... 52 jtag boundary scan................................................................. 53 memory map .................................................................................. 54 reading the memory map table.............................................. 54 global register map .................................................................. 56 input port register map ............................................................ 59 channel register map ............................................................... 62 output port register map ......................................................... 67 design notes ................................................................................... 70 outline dimensions ....................................................................... 72 ordering guide .......................................................................... 72 revision history 8/04revision 0: initial version
AD6636 rev. 0 | page 3 of 72 product description the AD6636 is a digital down-converter intended for if sampling or oversampled baseband radios requiring wide- bandwidth input signals. optimized for the demanding filtering requirements of wideband standards, such as cdma2000, umts, and td-scdma, the AD6636 is designed for radio systems that use either an if sampling adc or a baseband sampling adc. the AD6636 channels have the following signal processing stages: a frequency translator, a fifth-order cascaded integrated comb filter, two sets of cascaded fixed-coefficient fir and half- band filters, three cascaded programmable coefficient sum-of- product fir filters, an interpolating half-band filter (ihb), and a digital automatic gain control (agc) block. multiple modes are supported for clocking data into and out of the chip and provide flexibility for interfacing to a wide variety of digitizers. programming and control are accomplished via serial or microport interfaces. input ports can take input data at up to 150 msps. up to 300 msps input data can be supported using two input ports (some external interface logic is required) and two internal channels processing in tandem. biphase filtering in output data router is selected to complete the combined filtering mode. the four input ports can operate in cmos mode, or two ports can be combined for lvds input mode. the maximum input data rate for each input port is 150 mhz. frequency translation is accomplished with a 32-bit complex numerically controlled oscillator (nco). it has greater than 110 dbc sdfr. this stage translates either a real or complex input signal from if (intermediate frequency) to a baseband complex digital output. phase and amplitude dither can be enabled on-chip to improve spurious performance of the nco. a 16-bit phase-offset word is available to create a known phase relationship between multiple AD6636 chips or channels. the nco also can be bypassed so that baseband i and q inputs can be provided directly from baseband sampling adc through input ports. following frequency translation is a fifth-order cic filter with a programmable decimation between 1 and 32. this filter is used to lower the sample rate efficiently, while providing sufficient alias rejection at frequencies with higher frequency offsets from the signal of interest. following the cic5 are two sets of filters. each set has a non- decimating fir filter and a decimate-by-2 half-band filter. the fir1 filter provides about 30 db of rejection, while the hb1 filter provides about 77 db of rejection. they can be used together to achieve a 107 db stopband alias rejection, or they can be individually bypassed to save power. the fir2 filter provides about 30 db of rejection, while the hb2 filter provides about 65 db of rejection. the filters can be used either together to achieve more than 95 db stopband alias rejection, or can be individually bypassed to save power. fir1 and hb1 filters can run with a maximum input rate of 150 msps. in contrast, fir2 and hb2 can run with a maximum input rate of 75 msps (input rate to fir2 and hb2 filters). the programmable filtering is divided into three cascaded ram coefficient filters (rcfs) for flexible and power efficient filtering. the first filter in the cascade is the mrcf, consisting of a programmable nondecimating fir. it is followed by programmable fir filters (drcf) with decimation from 1 to 16. they can be used either together to provide high rejection filters, or independently to save power. the maximum input rate to the mrcf is one-fourth of pll clock rate. the crcf (channel rcf) is the last programmable fir filter with programmable decimation from 1 to 16. it typically is used to meet the spectral mask requirements for the air standard of interest. this could be an rrc, anti-aliasing filter or any other real data filter. decimation in preceding blocks is used to keep the input rate of this stage as low as possible for the best filter performance. the last filter stage in the chain is an interpolate-by-2 half-band filter, which is used to up-sample the crcf output to produce higher output oversampling. signal rejection requirements for this stage are relaxed because preceding filters already have filtered the blockers and adjacent carriers. each input port of the AD6636 has its own clock used for latching onto the input data, but input port a clock (clka) is used also as the input for an on-board pll clock multiplier. the output of the pll clock is used for processing all filters and processing blocks beyond the data router following cic filter. the pll clock can be programmed to have a maximum clock rate of 200 mhz. a data routing block (dr) is used to distribute data from the cics to the various channel filters. this block allows multiple back end filter chains to work together to process high bandwidth signals or to make even sharper filter transitions than a single channel can perform. it also can allow complex filtering operations to be achieved in the programmable filters. the digital agc provides the user with scaled digital outputs based on the rms level of the signal present at the output of the digital filters. the user can set the requested level and time constant of the agc loop for optimum performance of the postprocessor. this is a critical function in the base station for cdma applications where the power level must be well controlled going into the rake receivers. it has programmable clipping and rounding control to provide different output resolutions.
AD6636 rev. 0 | page 4 of 72 the overall filter response for the AD6636 is the composite of all the combined filter stages. each successive filter stage is capable of narrower transition bandwidths, but requires a greater number of clk cycles to calculate the output. more decimation in the first filter stage minimizes overall power consumption. data from the device is interfaced to a dsp/fpga/baseband processor via either high speed parallel ports (preferred) or a dsp-compatible microprocessor interface. the AD6636 is available both in 4-channel and 6-channel versions. the data sheet primarily discusses the 6-channel part. the only difference between the 6-channel and 4-channel devices is that on the 4-channel version, channels 4 and 5 are not available (see figure 1). the 4-channel device still has the same input ports, output ports, and memory map. the memory map section for channels 4 and 5 can be programmed and read back, but it serves no purpose. product highlights ? six independent digital filtering channels ? 101 db snr noise performance, 110 db spurious performance ? four input ports capable of 150 msps input data rates ? rms/peak power monitoring of input ports and 96 db range agcs before the output ports ? three programmable ram coefficient filters, three half- band filters, two fixed coefficient filters, and one fifth-order cic filter per channel ? complex filtering and biphase filtering (300 msps adc input) by combining filtering capability of multiple channels ? three 16-bit parallel output ports operating at up to 200 mhz clock ? blackfin?- and tigersharc?-compatible 16-bit microprocessor port ? synchronous serial communications port is compatible with most serial interface standards, sport, spi, and ssr
AD6636 rev. 0 | page 5 of 72 specifications table 1. recommended operating conditions parameter temp test level min typ max unit vddcore full iv 1.7 1.8 1.9 v vddio full iv 3.0 3.3 3.6 v t ambient full iv ?40 +25 +85 c electrical characteristics table 2. electrical characteristics 1 parameter temp test level min typ max unit logic inputs (not 5 v tolerant) logic compatibility full iv 3.3 v cmos logic 1 voltage full iv 2.0 3.6 v logic 0 voltage full iv ?0.3 +0.8 v logic 1 current full iv 1 10 a logic 0 current full iv 1 10 a input capacitance 25c v 4 pf logic outputs logic compatibility full iv 3.3 v cmos logic 1 voltage (i oh = 0.25 ma) full iv 2.0 vddio ? 0.2 v logic 0 voltage (i ol = 0.25 ma) full iv 0.2 0.4 v supply currents wcdma (61.44 mhz) example 1 i vddcore 25c v 450 ma i vddio 25c v 50 ma cdma 2000 (61.44 mhz) example 1 25c v i vddcore 25c v 400 ma i vddio 25c v 25 ma tds-cdma (76.8 mhz) example 1, 2 i vddcore 25c v 250 ma i vddio 25c v 15 ma gsm (65 mhz) example 1, 2 i vddcore 25c v 175 ma i vddio 25c v 10 ma total power dissipation wcdma (61.44 mhz) 1 25c v 975 mw cdma 2000 (61.44 mhz) 1 25c v 800 mw tds-cdma, (76.8 mhz) 1, 2 25c v 500 mw gsm, (65 mhz) 1, 2 25c v 350 mw 1 one input port, all six channels, and the relevant signal processing blocks are active. 2 pll is turned off for power savings.
AD6636 rev. 0 | page 6 of 72 general timing characteristics table 3. general timing characteristics 1, 2 parameter temp test level min typ max unit clk timing requirements t clk clkx period (x = a, b, c, d) full i 6.66 ns t clkl clkx width low (x = a, b, c, d) full iv 1.71 0.5 t clk ns t clkh clkx width high (x = a, b, c, d) full iv 1.70 0.5 t clk ns t clkskew clka to clkx skew (x = b, c, d) full iv t clk ? 1.3 ns input wideband data timing requirements full iv t si inx [15:0] to clkx setup time (x = a, b, c, d) full iv 0.75 ns t hi inx [15:0] to clkx hold time (x = a, b, c, d) full iv 1.13 ns t sexp expx [2:0] to clkx setup time (x = a, b, c, d) full iv 3.37 ns t hexp expx [2:0] to clkx hold time (x = a, b, c, d) full iv 1.11 ns t dexp clkx to expx[2:0] delay (x = a, b, c, d) full iv 5.98 10.74 ns parallel output port timing requirements (master) t dpreq pclk to px req delay (x = a, b, c) full iv 1.77 3.86 ns t dpp pclk to px [15:0] delay (x = a, b, c) full iv 2.07 5.29 ns t dpiq pclk to px iq delay (x = a, b, c) full iv 0.48 5.49 ns t dpch pclk to px ch[2:0] delay (x = a, b, c) full iv 0.38 5.35 ns t dpgain pclk to px gain delay (x = a, b, c) full iv 0.23 4.95 ns t spa px ack to pclk setup time (x = a, b, c) full iv 4.59 ns t hpa px ack to pclk hold time (x = a, b, c) full iv 0.90 ns parallel output port timing requirements (slave) t pclk pclk period full iv 5.0 ns t pclkl pclk low period full iv 1.7 0.5 t pclk ns t pclkh pclk high period full iv 0.7 0.5 t pclk ns t dpreq pclk to px req delay (x = a, b, c) full iv 4.72 8.87 ns t dpp pclk to px [15:0] delay (x = a, b, c) full iv 4.8 8.48 ns t dpiq pclk to px iq delay (x = a, b, c) full iv 4.83 10.94 ns t dpch pclk to px ch[2:0] delay (x = a, b, c) full iv 4.88 10.09 ns t dpgain pclk to px gain delay (x = a, b, c) full iv 5.08 11.49 ns t spa px ack to pclk setup time (x = a, b, c) full iv 6.09 ns t hpa px ack to pclk hold time (x = a, b, c) full iv 1.0 ns misc pins timing requirements t reset reset width low full iv 30 ns t dirp cpuclk/sclk to irp delay full v 7.5 ns t ss sync(0, 1, 2, 3) to clka setup time full iv 0.87 ns t hs sync(0, 1, 2, 3) to clka hold time full iv 0.67 ns 1 all timing specifications are valid over the vddcore range of 1.7 v to 1.9 v and the vddio range of 3.0 v to 3.6 v. 2 c load = 40 pf on all outputs, unless otherwise noted.
AD6636 rev. 0 | page 7 of 72 microport timing characteristics table 4. microport timing characteristics 1, 2 parameter temp test level min typ max unit microport clock timing requirements t cpuclk cpuclk period full iv 10.0 ns t cpuclkl cpuclk low time full iv 1.53 0.5 t cpuclk ns t cpuclkh cpuclk high time full iv 1.70 0.5 t cpuclk ns inm mode write timing (mode = 0) t sc control 3 to cpuclk setup time full iv 0.80 ns t hc control 3 to cpuclk hold time full iv 0.09 ns t sam address/data to cpuclk setup time full iv 0.76 ns t ham address/data to cpuclk hold time full iv 0.20 ns t drdy cpuclk to rdy ( dtack ) delay full iv 3.51 6.72 ns t acc write access time full iv 3 t cpuclk 9 t cpuclk ns inm mode read timing (mode = 0) t sc control 3 to cpuclk setup time full iv 1.00 ns t hc control 3 to cpuclk hold time full iv 0.03 ns t sam address to cpuclk setup time full iv 0.80 ns t ham address to cpuclk hold time full iv 0.20 ns t dd cpuclk to data delay full v 5.0 ns t drdy cpuclk to rdy ( dtack ) delay full iv 4.50 6.72 ns t acc read access time full iv 3 t cpuclk 9 t cpuclk ns mnm mode write timing (mode = 1) t sc control 3 to cpuclk setup time full iv 1.00 ns t hc control 3 to cpuclk hold time full iv 0.00 ns t sam address/data to cpuclk setup time full iv 0.00 ns t ham address/data to cpuclk hold time full iv 0.57 ns t ddtack cpuclk to dtack (rdy) delay full iv 4.10 5.72 ns t acc write access time full iv 3 t cpuclk 9 t cpuclk ns mnm mode read timing (mode = 1) t sc control 3 to cpuclk setup time full iv 1.00 ns t hc control 3 to cpuclk hold time full iv 0.00 ns t sam address to cpuclk setup time full iv 0.00 ns t ham address to cpuclk hold time full iv 0.57 ns t dd cpuclk to data delay full v 5.0 ns t ddtack cpuclk to dtack (rdy) delay full iv 4.20 6.03 ns t acc read access time full iv 3 t cpuclk 9 t cpuclk ns 1 all timing specifications are valid over the vddcore range of 1.7 v to 1.9 v and the vddio range of 3.0 v to 3.6 v. 2 c load = 40 pf on all outputs, unless otherwise noted. 3 specification pertains to control signals: r/ w ( wr ), ds ( rd ), and cs .
AD6636 rev. 0 | page 8 of 72 serial port timing characteristics table 5. serial port timing characteristics 1, 2 parameter temp test level min typ max unit serial port clock timing requirements t sclk sclk period full iv 10.0 ns t sclkl sclk low time full iv 1.60 0.5 t sclk ns t sclkh sclk high time full iv 1.60 0.5 t sclk ns spi port control timing requirements (mode = 0) t ssi sdi to sclk setup time full iv 1.30 ns t hsi sdi to sclk hold time full iv 0.40 ns t sscs scs to sclk setup time full iv 4.12 ns t hscs scs to sclk hold time full iv ?2.78 ns t dsdo sclk to sdo delay time full iv 4.28 7.96 ns sport mode control timing requirements (mode = 1) t ssi sdi to sclk setup time full iv 0.80 ns t hsi sdi to sclk hold time full iv 0.40 ns t ssrfs srfs to sclk setup time full iv 1.60 ns t hsrfs srfs to sclk hold time full iv ?0.13 ns t sstfs stfs to sclk setup time full iv 1.60 ns t hstfs stfs to sclk hold time full iv ?0.30 ns t sscs scs to sclk setup time full iv 4.12 ns t hscs scs to sclk hold time full iv ?2.76 ns t dsdo sclk to sdo delay time full iv 4.29 7.95 ns 1 all timing specifications are valid over the vddcore range of 1.7 v to 1.9 v and the vddio range of 3.0 v to 3.6 v. 2 c load = 40 pf on all outputs, unless otherwise noted. explanation of test levels for specifications i 100% production tested. ii 100% production tested at 25c, and s ample tested at specified temperatures. iii sample tested only. iv parameter guaranteed by design and analysis. v parameter is typical value only. vi 100% production tested at 25c, and sampled tested at temperature extremes.
AD6636 rev. 0 | page 9 of 7 2 absolute maximum ra tings table 6. p a r a m e t e r r a t i n g electr i c a l vddcore supply voltage (core supply) 2.2 v vddio supply voltage (ring or io supply) 4.0 v input voltage ?0.3 to +3.6 v ( n ot 5 v tolerant) output voltage ?0.3 to vddio + 0.3 v load capacitance 200 pf environ m en t a l operating temperature range (ambient) ?40c to +85c maximum junction temperature under bias 125c storage temperature range (ambient) ?65 c to +150c s t r e s s es a b o v e t h os e lis t e d u n de r t h e a b s o l u t e m a xim u m r a tin g s m a y ca use pe rm a n en t d a ma g e t o t h e devi ce . t h is i s a st re ss r a t i n g on l y ; f u nc t i on a l op e r a t i o n of t h e d e v i c e a t t h e s e or a n y o t h e r con d i t io n s ab o v e t h o s e i n dica t e d in t h e op era t io nal s e c t io n o f t h is sp e c if ic a t io n is no t im plie d . e x p o sur e t o a b s o l u te max i m u m ra t i ng co ndi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vice r e l i ab i l i t y . thermal c h ar a c teristics 256-bal l cs p_ b g a p a c k a g e: ja = 25.4c /w , n o a i r f lo w ja = 23.3c /w , 0.5 m/s air f lo w ja = 22.6c /w , 1.0 m/s air f lo w ja = 21.9c /w , 2.0 m/s air f lo w ther mal m e as u r em e n ts made i n t h e h o r i zon t al p o si t i o n on a 4-la yer bo a r d wi th vias. esd c a ution esd (electrostatic discharge) sensitive device. ele c tros tatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge wi thout detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
AD6636 rev. 0 | page 10 of 72 pin conf igura t ion and fu nction descriptions 1 2 34 56 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 a gnd inc3 ind4 ind7 clkd clkc ind11 gnd vddcore ind14 ind15 sync1 tdo pbgain pb11 gnd a b ind0 vddio inc2 ind5 ind6 ind8 ind10 ind12 ind13 inc14 sync3 sync0 trst pbch2 vddio pb12 b c expa1 expd1 inc0 inc1 ind3 inc5 ind9 inc10 inc13 sync2 tms tclk pbch0 pb8 pb15 pb10 c d expb0 expc2 expc1 expd0 ind2 inc4 inc7 inc9 inc12 tdi pbch1 pbiq pb14 pb9 pb13 pach1 d e ina14 ina15 expa0 lvds_rset gnd ind1 inc6 inc8 inc11 inc15 pbreq pback pb4 pb5 pb1 pclk e f ina12 ina13 expb1 expc0 expd2 gnd vddio vddio vddio vddio gnd pb6 pb0 pb7 pareq pa0 f g ina11 inb13 inb15 expb2 expa2 vddcore gnd gnd gnd gnd vddcore pb3 pagain pb2 pach0 pa2 g h vddcore ina10 inb12 inb11 inb14 vddcore gnd gnd gnd gnd vddcore pach2 paiq paack pa1 gnd h j gnd ina9 inb10 inb8 inb9 vddcore gnd gnd gnd gnd vddcore pa3 pa7 pa5 pa4 vddcore j k clka ina8 ina7 inb6 inb7 vddcore gnd gnd gnd gnd vddcore pa12 pa15 pa9 pa8 pa6 k l clkb ina6 inb4 inb1 inb3 gnd vddio vddio vddio vddio gnd pc3 pcack pcch1 pa13 pa10 l r cpuclk (sclk) vddio msb_ first ext_ filter chipid1 d14 d10 d11 d6 d0 a3 a1 pc9 pc6 vddio pcreq r 1 2 34 56 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 = vddcore = vddio = ground 04998-0-002 m ina5 inb5 inb2 inb0 gnd d13 d15 d5 a5 pc12 pc7 pc2 pc0 pcch0 pa11 m dtack (rdy, sdo) n ina4 ina3 ina0 chipid2 d12 d2 d1 a4 a0 (sdi) pc15 pc5 pc1 pcch2 pa14 n r/w (wr, stfs) cs (scs) p ina2 ina1 smode chipid3 gnd d9 d4 a6 a2 pc11 pc10 pc4 pciq pcgain p ds (rd, srfs) reset t gnd mode chipid0 d7 d8 d3 vddcore gnd gnd a7 pc14 pc13 pc8 gnd gnd t irp f i gure 2. cs p_bg a p i n configu r ation ta ble 7. pi n na mes a n d f u nct i ons n a m e t y p e p i n n o . f u n c t i o n power supply vddcore power see table 8 1.8 v digital core supply. vddio power see table 8 3.3 v digital i/o supply. gnd ground see table 8 digital core and i/o ground. input ( adc) p o rts (cmo s/lvds) c l k a i n p u t k 1 clock for input port a. used to clock in a[15:0] and expa[2: 0] data. additionally, this clock is used to drive intern al circuitry and pll clock multiplier. clkb input l1 clock for input port b. used to cl ock inb[15:0] and expb[2:0 ] da ta. clkc input a6 clock for input port c. us ed to c l ock inc[15:0] and expc [2:0] data. clkd input a5 clock for input port d. us ed to clock ind[15:0] and expd[2:0 ] d a ta. ina[0:15 ] input see table 8 input port a (pa r alle l). inb[0:15] input see table 8 input port b (par alle l). inc[0:15] input see table 8 input port c (paralle l). ind[0:15] input see table 8 input port d (paralle l). expa[0:2 ] bidirectional e3, c1, g5 exponent bus input port a. gain control output. expb[0:2] bidirectional d1, f3, g4 expone n t bus input port b. gain control output. expc[0:2 ] bidirectional f4, d3, d2 expone n t bus input port c. gain control output. expd[0:2 ] bidirectional d4, c2, f5 expone n t bus input port d. gain control output. clka, clkb input k1, l1 lvds differentia l clock fo r lvds _a input port (l vds_clka+, lv ds_clka?).
AD6636 rev. 0 | page 11 of 72 name type pin no. function clkc, clkd input a6, a5 lvds differential clock for lvds_c input port (lvds_clkc+, lvds_clkc?). ina[0:15], inb[0:15] lvds input see table 8 in lvds input mode, ina[0 :15] and inb[0 :15] form a differential pair lvds_a+[0:15] (positive node) and lvds_a C[0:15] (negative node), respectively. inc[0:15], ind[0:15] lvds input see table 8 in lvds input mode, inc[0 :15] and ind[0 :15] form a differential pair lvds_c+[0:15] (positive node) and lvds_cC[ 0:15] (negative node), respectively. output ports pclk bidirectional e16 parallel output port cloc k. master mode output, slave mode input. pa[0:15] output see table 8 parallel output port a data bus. pach[0:2] output g15, d16, h12 ch annel indicator output port a. paiq output h13 parallel port a i/q data indica tor. logic 1 indicates i data on data bus. pagain output g13 parallel port a gain word output indicator. logic 1 indicates gain word on data bus. paack input h14 parallel port a acknowledge (active high). pareq output f15 parallel port a request (active high). pb[0:15] output see table 8 para llel output port b data bus. pbch[0:2] output c13, d11, b14 ch annel indicator output port b. pbiq output d12 parallel port b i/q data indicator. logic 1 indi cates i data on data bus. pbgain output a14 parallel port b gain word output indica tor. logic 1 indicates gain word on data bus. pback input e12 parallel port b acknowledge (active high). pbreq output e11 parallel port b request (active high). pc[0:15] output see table 8 para llel output port c data bus. pcch[0:2] output m15, l14, n15 ch annel indicator output port c. pciq output p15 parallel port c i/q data indicator. logic 1 indicates i data on data bus. pcgain output p16 parallel port c gain word output indica tor. logic 1 indicates gain word on data bus. pcack input l13 parallel port c acknowledge (active high). pcreq output r16 parallel port c request (active high). misc pins reset input p3 master reset (active low). irp output t2 interrupt pin. sync[0:3] input b12, a12, c10, b11 synchronization inputs. sync pins are in dependent of channels or input ports and independent of each other. lvds_rset input e4 lvds resistor set pin (analog pin). see design notes. ext_filter input r4 pll loop filter (analog pin). see design notes. microport control d[0:15] bidirectional see table 8 bidirectional microport data. this bus is three-stated when cs is high. a[0:7] input see table 8 microport address bus. ds ( rd ) input p4 active low data strobe when mode = 1. active low read strobe when mode = 0. dtack (rdy) 1 output m6 active low data ac knowledge when mode = 1. microport status pin when mode = 0. r/ w ( wr ) input n4 read/write strobe when mode = 1. active low write strobe when mode = 0. mode input t3 mode select pin. when smode = 0: logic 0 = intel mode; logic 1 = motorola mode. when smode = 1: logic 0 = spi mode; logic 1 = sport mode. cs input n5 active low chip select. logic 1 three-states the microport data bus. cpuclk input r1 microport clk input (input only). chipid[0:3] input t4, r5, n6, p6 chip id input pins.
AD6636 rev. 0 | page 12 of 72 name type pin no. function serial port control sclk input r1 serial clock. sdo output m6 serial port data output. sdi 2 input n11 serial port data input. stfs input n4 serial transmit frame sync. srfs input p4 serial receive frame sync. scs input n5 serial chip select. msb_first input r3 select msb first into sdi pin and msb first out of sdo pin. logic 0 = msb first; logic 1 = lsb first. smode input p5 serial mode select. pull high when serial port is used and low when microport is used. jtag trst 1 input b13 test reset pin. pull low when jtag is not used. tclk 2 input c12 test clock. tms 1 input c11 test mode select. tdo output a13 test data output. thr ee-stated when jtag is in reset. tdi 1 input d10 test data input. 1 pin with a pull-up resistor of nominal 70 k? . 2 pin with a pull-down resistor of nominal 70 k? . pin listing for power, ground, data and address buses table 8. name pin no. vddcore a9, g6, g11, h1, h6, h11, j6, j11, j16, k6, k11, t8 vddio b2, b15, f7, f8, f9, f10, l7, l8, l9, l10, r2, r15 gnd a1, a8, a16, e5, f6, f11, g7, g8, g9, g10, h7, h8, h9, h10, h16, j1, j7, j8, j9, j10, k7, k8, k9, k10, l6, l11, m5, p7, t1, t9, t10, t15, t16 ina[0:15] n3, p2, p1, n2, n1, m1, l2, k3, k2, j2, h2, g1, f1, f2, e1, e2 inb[0:15] m4, l4, m3, l5, l3, m2, k4, k5, j4, j5, j3, h4, h3, g2, h5, g3 inc[0:15] c3, c4, b3, a2, d6, c6, e7, d7, e8, d8, c8, e9, d9, c9, b10, e10 ind[0:15] b1, e6, d5, c5, a3, b4, b5, a4, b6, c7, b7, a7, b8, b9, a10, a11 pa[0:15] f16, h15, g16, j12, j15, j14, k16, j 13, k15, k14, l16, m16, k12, l15, n16, k13 pb[0:15] f13, e15, g14, g12, e13, e14, f12, f14, c14, d14, c16, a15, b16, d15, d13, c15 pc[0:15] m14, n14, m13, l12, p14, n13, r14, m12, t14, r13, p13, p12, m11, t13, t12, n12 d[0:15] r10, n9, n8, t7, p9, m9, r9, t5, t6, p8, r7, r8, n7, m7, r6, m8 a[0:7] n11, r12, p11, r11, n10, m10, p10, t11
AD6636 rev. 0 | page 13 of 72 timing diagrams 04998-0-003 reset t resl f i gur e 3 . re se t t i m i ng re quir em e n ts c lk x t clkh t clkl 04998-0-004 f i gure 4 . cl k s w it chi n g ch a r a c teri sti c s (x = a, b , c, d for in div i dual input p o r t s) clk a t clkskew clkx t clk t clkl t clkh 04998-0-005 f i gure 5. cl k sk ew char acteristics (x = b , c, d fo r ind i v i dual i n put p o r t s) cpuclk t cpuclkl t cpuclkh 04998-0-006 f i g u re 6. c p u c lk switc h ing c h a r ac ter i s t ics sclk t sclkh t sclkl 04998-0-007 f i g u re 7. scl k sw it ching c h a r ac ter i s t i c s s ync [3:0] clka t hsync t ssync 04998-0-008 fi g u r e 8 . s y n c t i m i n g i n p u t s
AD6636 rev. 0 | page 14 of 72 expx[2:0] clkx t dexp t clk t clkl t clkh 04998-0-009 f i g u re 9. g a in cont r o l w o r d o u t p ut switc h ing c h a r ac ter i s t ics (x = a , b , c, d for in dividual input p o r t s) inx[15:0] clkx expx[15:0] t hi t si t sexp t hexp 04998-0-010 f i gure 10. input p o r t ti ming f o r d a ta (x = a , b , c, d for in dividual input p o r t s) 04998-0-011 pclk t dpreq pxreq pxack px [15:0] pxiq pxch [2:0] pxgain i [15:0] q [15:0] i [15:0] q [15:0] rssi [11:0] rssi [11:0] pxch [2:0] = channel # pxch [2:0] = channel # t dpgain t dpp t dpp t dpp t dpiq t dpch t dpp t dpiq t dpch t dpgain t spa t dpp t dpp t hpa f i g u re 11. m a s t e r m o de px a c k to pc lk swi t ch ing ch ar ac te ris t i c s (x = a, b , c, d for in div i dual o u tput p o r t s)
AD6636 rev. 0 | page 15 of 72 pclk t dpreq pxreq pxack px [15:0] pxiq pxch [2:0] pxgain tied logic high all the time i [15:0] q [15:0] i [15:0] q [15:0] rssi [11:0] rssi [11:0] pxch [2:0] = channel # pxch [2:0] = channel # t dpgain t dpp t dpp t dpp t dpiq t dpch t dpp t dpiq t dpch t dpgain t dpp t dpp 04998-0-012 f i g u re 12. m a s t e r m o de px r e q to pc lk swi t ch ing ch ar ac te ris t i c s t sam rd wr cs a [7:0] d [15:0] rdy valid address valid data t ham cpuclk note: t acc access time depends on the address accessed. it can vary from 3 to 9 cpuclk cycles. t sc t sc t sam t drdy t ham t hc t hc t acc 04998-0-013 f i gure 13. inm m i c r opo r t write ti min g r e quire m ents
AD6636 rev. 0 | page 16 of 72 rd wr cs a [7:0] d [15:0] rdy valid address valid data cpuclk t sc t sc t sam t dd t drdy t hc t hc t ham note: t acc access time depends on the address accessed. it can vary from 3 to 9 cpuclk cycles. t acc 04998-0-014 f i gure 14. inm m i cropo r t r e ad ti ming r e quirem ents t sam ds r/w cs a [7:0] d [15:0] dtack valid address valid data t sam t ham t ddtack note: t acc access time depends on the address accessed. it can vary from 3 to 9 cpuclk cycles. t sc t hc cpucl k t hc t hc t ham t sc t sc 04998-0-015 t acc f i gure 15. mnm m i cropo r t w r i t e t i m i ng r e qui r e m ents
AD6636 rev. 0 | page 17 of 72 04998-0-016 t sam ds r/w cs a [7:0] d [15:0] valid address valid data t ham t ddtack note: t acc access time depends on the address accessed. it can vary from 3 to 9 cpuclk cycles. t hc cpucl k t hc t hc t dd t sc dtack t sc t sc t acc f i g u r e 1 6 mn m mi cr o p o r t r e a d t i m i ng r e q u i r em e n t s scs smode sdi mode t sscs t hsi t ssi t hscs logic 1 logic 1 sclk t hsrfs t ssrfs d0 d1 d2 d3 d4 d5 d6 d7 srfs 04998-0-017 f i g u re 17. sport m o de w r ite ti m i ng c h ar ac t e ris t i c s
AD6636 rev. 0 | page 18 of 72 scs smode sdo mode t sscs t dsdo t hscs logic 1 logic 1 sclk t hstfs t sstfs stfs d0 d1 d2 d3 d4 d5 d6 d7 04998-0-018 f i g u re 18. sport m o de r e ad ti mi ng c h ar ac t e ris t i c s scs smode sdi mode t sscs t hsi d0 d1 d2 d3 d4 d5 d6 d7 t ssi t hscs logic 1 logic 0 sclk 04998-0-019 f i gure 19. spi mod e write ti ming c h a r ac ter i stics sclk scs smode sdo mode t sscs t dsdo d0 d1 d2 d3 d4 d5 d6 d7 t hscs logic 0 logic 0 04998-0-020 f i gure 20. spi mod e read tim i ng ch a r ac ter i stics
AD6636 rev. 0 | page 19 of 72 theor y of opera tion adc i n pu t port the AD6636 f e a t ur es f o ur iden tical , in dep e n d en t hig h sp ee d ad c i n p u t p o r t s na me d a, b , c, a nd d . t h es e i n p u t p o r t s ha ve t h e f l exi b i l i t y t o al lo w in dep e n d en t i n p u t s , di v e rsi t y in p u ts, o r co m p lex i/q in p u ts. a n y o f t h e ad c in p u t p o r t s can b e r o u t e d t o a n y o f the six t u n e r c h a n n e ls; tha t is, an y o f th e six AD6636 c h a n n e ls can r e cei v e in p u t da t a f r o m a n y o f th e in p u t p o r t s. t i m e -m u l t i p l exed in p u ts on a s i n g le p o r t a r e no t s u p p o r t e d in th e AD6636. th es e f o ur in p u t p o r t s can o p er a t e a t u p t o 150 ms ps. e a c h in p u t p o r t has i t s o w n clo c k (c l k a, cl kb , cl k c , a nd cl kd) us ed f o r r e g i s t er in g in p u t da ta in t o the AD6636 . t o al lo w s l o w in p u t ra t e s w h i l e p r o v iding fast p r o c essin g clo c k ra t e s, t h e AD6636 co n t a i n s a n in t e r n al pll c l o c k m u l t i p lier tha t s u p p lies th e in t e r n al sig n al p r o c es sin g clo c k. cl k a is us ed as a n in p u t to th e pl l c l oc k m u l t i p li e r . a d di ti o n al p r ogra m m a b i li t y allo w s th e in p u t da t a t o b e clo c k e d in t o t h e p a r t ei t h er on t h e r i sin g e d ge or t h e f a l l i n g e d ge of t h e i n put c l o c k . i n addi tion, t h e f r o n t end o f th e AD6636 co n t a i n s cir c ui tr y tha t ena b les hig h sp e e d sig n a l -le v el dete c t ion, ga in co n t r o l, a nd q u adr a t u r e i / q co r r e c t i o n . this is acco m p lish e d w i t h a uniq u e hig h sp e e d le vel - dete c t ion cir c u i t t h a t o f fers minima l l a te n c y a nd max i m u m f l ex i b i l i t y to co n t r o l a l l fo ur in p u t sig n a l s (t yp i c all y ad c i n p u t s ) in d i vid u all y . t h e in p u t p o r t s also prov i d e i n put p o we r - mon i tor i n g f u nc t i ons v i a v a r i ou s mo d e s , a nd ma g n i t ude a nd phas e i/q c o r r e c t i o n b l o c ks. s e e t h e qu a d r a t u r e i / q c o rr ecti o n b l oc k secti o n f o r d e ta il s . e a ch i n d i vi d u a l p r o c essin g channel can r e cei v e in p u t d a t a f r o m a n y o f t h e fo ur i n p u t p o r t s indivi d u a l ly . this is co n t r o l l e d using 3-b i t cr ossb a r m u x-s e le c t b i t w o r d s in ad c i n p u t con t r o l r e g i ster . e a ch i ndivid u a l cha n nel has a sim i la r 3 - b i t s e le c t io n. i n a ddit i on to t h e f o u r i n put p o r t s , an i n te r n a l te s t s i g n a l ( p n p s e u d o r a nd o m noi s e s e qu e n c e ) c a n a l s o b e s e l e c t e d . t h i s in t e r n a l t e st sig n a l is dis c uss e d in t h e u s er -c o n f i gura b l e bui l t- in s e l f - t e s t ( b i s t ) s e c t i o n . input d a ta f o rmat e a ch in p u t p o r t co n s ists o f a 16 -b i t man t iss a and a 3- b i t exp o n e n t (16 + 3 f l o a tin g -p o i n t in p u t, o r u p t o 16-b i t f i xed- p o in t in p u t). w h e n in t e r f acin g t o st anda r d f i xe d-p o in t a d cs, t h e exp o n e n t b i t s h o u l d ei t h er b e co nne c t e d t o g r o u n d o r b e p r ogra mm e d as o u t p u t s f o r ga in co n t r o l o u t p u t . i f co n n e ct e d to a f l o a t i ng - p o i n t a d c ( a l s o c a l l e d g a i n r a ng i n g a d c ) , t h e exp o n e n t b i ts f r o m t h e a d c c a n b e co nn e c te d t o t h e i n p u t exp o n e n t b i ts o f th e AD6636. th e ma n t is s a da t a f o r m a t is tw os c o m p l e m e nt , a n d t h e e x p o n e nt i s u n s i g n e d bi n a r y . the 3-exp o n e n t b i t s a r e s h a r e d wi t h t h e ga i n ran g e co n t r o l b i ts i n t h e h a rd w a re. w h e n f l o a t i ng - p oi n t a d c s are not u s e d , t h e s e t h re e pi ns o n e a c h a d c i n put p o r t c a n b e u s e d a s g a i n r a ng e co n t r o l o u t p u t b i ts. input t i ming the da t a f r o m e a ch hig h s p e e d i n p u t p o r t is la t c h e d ei t h er on th e ri si n g ed ge o r th e falli n g edg e o f th e po r t s in di v i d u al c l k x (wh e r e x s t an ds f o r a, b , c, o r d in p u t p o r t s). the ad c c l o c k in v e r t b i t in ad c clo c k co n t r o l r e g i s t er s e le c t s t h e e d g e o f t h e clo c k (r isin g o r fa l l in g) us e d t o r e g i st er in p u t d a t a in t o t h e AD6636. inx [15:0] expx [2:0] clkx data n data n + 1 04998-0-021 t si t hi f i gure 2 1 . input d a ta t i m i ng requir em ents (r ising edge of c l o c k , x = a, b , c , o r d for f o u r input p o r t s) inx [15:0] expx [2:0] clkx data n data n + 1 04998-0-022 t si t hi f i gure 2 2 . input d a ta t i m i ng requir em ents (f all i ng edge of c l o c k , x = a, b , c , o r d for f o u r input p o r t s) the clo c k sig n a l s (clk a, cl k b , clk c , and c l kd) c a n o p era t e a t u p t o 150 mh z. i n a p p l ica t ion s usin g hig h sp ee d ad cs, t h e ad c s a m p le clo c k, da t a v a lid , o r da t a r e ad y s t r o b e a r e typ i cal l y us e d t o c l o c k t h e AD6636. c o nnec t i o n to f i x e d-p o int ad c f o r f i xed-p o in t ad cs, t h e ad6 636 exp o n e n t in p u ts, exp[2:0], a r e n o t typ i ca l l y us e d an d sh o u l d b e t i e d lo w . a l t e r n a t i v e l y , b e ca us e t h es e p i n s a r e s h a r e d wi t h ga in ran g e con t r o l b i ts, if t h e ga in ra n g in g b l o c k is us ed , t h es e p i n s ca n be us ed as o u t p u t s o f t h e ga i n ra n g e c o n t r o l b l o c k. the ad c o u t p u t s a r e t i e d dir e c t l y t o th e AD6636 in p u ts, ms b - j u s t if ied . th er ef o r e , f o r f i xed-p o in t ad cs, t h e exp o n e n t s a r e typ i c a l l y s t a t ic and n o in p u t s c ali n g is us ed in t h e AD6636. f i gur e 23 s h o w s a typ i cal in t e r c o n nec t io n.
AD6636 rev. 0 | page 20 of 72 04998-0-023 ad6 6 4 5 14-bit adc a d 66 36 d13 (msb) d0 (lsb) in15 in2 exp0 exp1 in0 in1 exp2 gain ranging control bits or grounded exponent bits f i g u re 23. t y pic a l i n terc on nec t i o n of t h e a d 6 6 45 f i x e d- p o int a d c and t h e a d 6 6 36 s c aling with f l oating-p oint a d c an exa m ple o f t h e exp o n e n t con t r o l fe a t ur e com b i n es t h e ad6600 an d t h e AD6636. the ad6600 is an 11-b i t ad c wi th t h r e e b i ts o f ga i n ra n g ing. i n ef fe c t , t h e 11 -b i t a d c p r o v ides t h e m a n t i s s a , a n d t h e t h re e bit s of t h e re l a t i ve s i g n a l st re ng t h indic a t o r (rss i) a r e t h e exp o n e n t . onl y f i v e o f t h e ei g h t a v a i la b l e st eps ar e us ed b y th e ad6600. s e e t h e ad6600 da t a she e t for de t a i l s . table 9. weigh t ing factors for different e x p[2:0 ] values adc input lev e l ad66 36 exp[2:0] data divid e -b y signal attenuation ( d b) largest 000 (0) /1 (>> 0) 0 001 (1) /2 (>>1) 6 010 (2) /4 (>>2) 12 011 (3) /8 (>>3) 18 100 (4) /16 (>> 4) 24 101 (5) /32 (>> 5) 30 110 (6) /64 (>> 6) 36 smalle st 111 (7) /128(>> 7) 42 c o mplex (i/q) inpu t p o r t s the f o ur individ u al ad c in p u t p o r t s o f th e AD6636 can b e co nf igur e d to f u n c t i on as tw o c o m p lex in p u t p o r t s. a ddi t i ona l ly , if r e q u ir e d , o n ly tw o in p u t p o r t s ca n b e m a de t o f u n c t i on as a co m p le x po r t , w h ile th e r e m a i n in g t w o in p u t po r t s fun c ti o n a s r e al i n d i vi d u al in p u t po r t s. in c o mp l e x m o d e , inp u t p o r t a i s p a i r e d w i t h i n p u t p o r t b t o re c e ive i a n d q d a t a , re sp e c t i vel y . si m i l a r l y , in p u t p o r t c c a n b e p a ir ed wi t h i n p u t p o r t d t o r e c e i v e i an d q da t a , r e s p ec ti ve l y . th e s e t w o p a ir in gs a r e co n t r o l l e d i n d i vid u a l ly usin g bi ts 24 and 2 5 of a d c i n put c o n t ro l re g i ste r . a s ex plaine d p r e v i o u sly , e a ch i ndivid u a l cha n nel ca n r e ce i v e in p u t sig n als f r o m an y o f th e four in p u t p o r t s u s in g the cr os sbar m u x se lect b i t s in th e ad c in p u t co n t r o l r e gi s t er . i n a d di ti o n t o t h e t h r e e b i ts, a 1-b i t s e le c t io n i s p r o v ide d fo r ch o o sin g t h e c o m p l e x i n put p o r t opt i on f o r an y i n d i v i du a l c h an nel. f o r exa m p l e , if channe l 0 n eeds t o r e cei v e com p lex in p u t f r o m i n p u t p o r t s a and b , t h e n t h e m u x s e le c t b i ts sh o u ld i n di ca te i n p u t p o r t a, and t h e co m p lex i n p u t b i t sh o u ld b e s e le c t e d . w h en t h e in p u t p o r t s a r e p a ir e d fo r co m p lex in p u t op era t ion, o n l y o n e s e t o f exp o n e n t b i ts is dr i v en ext e r n al l y wi t h gain co n t r o l o u t p u t . s o w h en i n pu t p o r t s a an d b fo r m a co m p lex i n p u t, th en ex p a [2:0] a r e o u t p u t a n d , si mila r l y , f o r i n p u t p o r t s c a n d d , ex pc[2:0] a r e o u t p u t . lv d s i n p u t p o r t s AD6636 in p u t p o r t s ca n be conf igur ed in tw o dif f er en t m o des : cmos o r l v ds. i n cmos in p u t m o de , t h e fo ur in p u t p o r t s can b e co nf igur e d a s tw o co m p lex i n p u t p o r t s. i n l v ds m o de , tw o cm os in p u t p o r t s eac h a r e com b in e d t o f o r m o n e l v ds in p u t po r t . cm os i n p u t p o r t s in a[15:0] a nd inb[15:0] f o r m th e p o si t i v e a nd n e g a t i ve dif f er en t i a l n o des, l v ds_a+[ 15:0 ] a n d l v ds_a?[15:0 ] , r e s p ec ti v e l y . s i mila rl y , inc[15:0] a n d ind[15:0] f o r m th e p o si t i v e and n e ga t i v e dif f er en t i al n o des, l v ds_c+[15:0 ] a n d l v ds_c? [15:0], r e s p ec ti v e l y . cl k a and clkb fo r m t h e dif f er en t i al p a ir , l v ds_cl k a+ a nd l v ds_cl k a? p i n s . s i mila rl y , clk c an d c l kd f o r m th e d i f f e r e n ti al pa i r l v d s _ c lk c + a n d l v d s _c lk c ? p i n s . b y defa u l t, t h e AD6636 p o w e rs u p in cm os mo de an d can b e p r og ra mm e d t o cm os m o de b y usin g th e cmos m o de b i t (bi t 10 o f th e l v ds co n t r o l r e g i s t er) . w r i t in g l o g i c 1 t o b i t 8 o f th e l v ds co n t r o l r e g i s t er enab les an a u t o calib r a t e r o u t in e tha t calib r a t es t h e i m p e dance o f t h e l v ds p a ds t o ma t c h t h e o u t p u t im p e dan c e o f t h e l v ds sig n al s o ur ce im p e dance . th e l v ds p a ds in t h e AD6636 ha v e an in t e r n al im p e dance o f 100 ? acr o s s t h e dif f er en t i a l sig n als; t h er efo r e , a n ext e r n al r e sis t o r is n o t re qu i r e d . pll cl ock mul t iplier i n t h e AD6636, th e in p u t c l o c k ra t e m u s t be t h e s a me as t h e in p u t da t a ra te . i n a typ i c a l dig i t a l do w n -con v e r t er a r chi t e c t u r e , t h e clo c k ra te is a limi t a t i o n on t h e n u m b er o f f i l t er t a ps t h a t ca n b e calc u l a t e d in t h e p r og ra mma b l e r a m c o ef f i cien t f i l t ers (mr c f , d r c f , a nd crcf). f o r s l o w er ad c clo c k ra t e s (o r fo r a n y c l oc k ra t e ), th i s li m i t a ti o n ca n be o v e r co m e b y usi n g a p l l clo c k m u l t i p lier t o p r o v ide a hig h er clo c k r a t e to t h e r c f f i l t ers. u s i n g t h i s c l oc k m u l t i p li er , th e in t e rn al si gn al p r oces si n g c l oc k ra t e c a n be in cr eas e d u p t o 200 mh z. the cl k a sig n al is us ed as a n i n p u t t o t h e pll clo c k m u l t i p lier . 04998-0-024 clk a pll_clk adc_clk divide by n (1, 2, 4 or 8) pll clock mulitplier (4x to 20x) pll clock generation bypass_pll 1 for bypass nm 2 5 0 1 1 0 f i g u re 24. pll c l o c k gene r a t i on
AD6636 rev. 0 | page 21 of 72 the p ll clo c k m u l t i p lier is p r o g ra mma b l e and us es in p u t clo c k ra t e s betw een 4 mh z and 150 mh z t o g i v e a s y s t em c l o c k r a t e (o u t p u t) o f as hig h as 200 m h z. the o u t p u t c l o c k ra t e is g i v e n b y n m clka clk pll = _ wher e: cl k a is t h e i n pu t p o r t a clo c k ra t e . m i s a 5 - bi t pro g r a mmabl e m u lt i p l i c a t i on f a c t or . n is a p r e d ivide fac t o r . m is a 5-b i t n u m b er betw een 4 a n d 20 (bo t h val u es in c l u d ed). n (p r e di vide) c a n be 1, 2, 4, o r 8. th e m u l t i p lic a tion fac t o r m is p r og ra mm e d usin g a 5- b i t p l l clo c k m u l t i p lier w o r d in t h e ad c clo c k co n t r o l r e g i st er . a val u e o u tside t h e valid ra n g e o f 4 t o 20 b y p a ss es t h e pll clo c k m u l t i p lier an d , t h er efo r e , t h e p l l clo c k is t h e s a me as t h e i n p u t cl o c k. th e p r e d ivi d e fac t o r n is pro g r a m m e d u s i n g a 2 - bit a d c pre - p l l c l o c k d i v i d e r word i n th e ad c c l o c k co n t r o l r e g i s t er , as lis t e d in t a b l e 10. table 10. pl l clock generation pre d ivider control predivi d e wor d [1:0] divid e -by val u e for the clock 0 0 d i v i d e - b y - 1 , b y p a s s 0 1 d i v i d e - b y - 2 1 0 d i v i d e - b y - 4 1 1 d i v i d e - b y - 8 f o r b e st sig n al p r o c essin g ad van t a g e , t h e us er sh o u ld p r og ra m t h e clo c k m u l t i p lier t o g i v e a sy st em clo c k o u t p u t as clos e as p o s s i b le t o , b u t n o t excee d ing, 200 mh z. the in t e r n al b l o c ks o f th e AD6636 tha t r u n o f f o f th e p ll c l o c k a r e r a t e d t o r u n a t a m a xim u m o f 200 mh z. the def a u l t p o w e r - u p sta t e fo r th e p ll clo c k m u l t i p lier is t h e b y p a ss st a t e , wher e cl k a is p a ss e d o n as t h e pll clo c k. adc gain c o ntrol e a c h ad c in p u t po r t h a s in di vid u al , h i gh spee d ga i n - c o n tr o l log i c cir c ui tr y . s u c h ga in-co n tr ol cir c ui tr y is us e f u l in a p p l ic a - t i o n s t h a t i n v o lve la rg e d y na mic - ra n g e i n p u t s o r in w h ich ga in-ran g i n g ad cs a r e em p l o y ed . th e AD6636 ga in-con tr ol log i c al l o ws p r o g ra m m a b l e u p p e r a n d lo w e r thr e s h o l ds and a p r ogra m m a b l e d w e l l-tim e co un t e r f o r t e m p o r al h y s t er esis. e a c h in p u t p o r t has a 3-b i t o u t p u t f r o m th e gain co n t r o l b l o c k. th e s e t h r e e o u t p u t p i ns a r e shar e d wi t h t h e 3 - b i t exp o n e n t i n pu t pi ns f o r e a c h i n put p o r t . t h e op e r a t i o n i s c o n t ro l l e d by th e ga in co n t r o l ena b le b i t in gain co n t r o l r e g i s t er o f th e indivi d u a l i n p u t p o r t s. a l o g i c 1 in t h is b i t p r og ra m s t h e exp[ 2:0] p i n s a s gain-c on t r ol ou t p uts, an d a l o g i c 0 c o nf igur es t h e pin s as in pu t exp o n e n t pin s . t o a v o i d b u s co n t e n t i o n , t h es e p i n s a r e set, b y d e fa ul t, as in p u t exp o n e n t p i n s . fu n c t i o n the gai n -c on t r ol bl o c k fe a t ur es a p r o g r a mmabl e u p p e r t h re sho l d re g i s t e r an d a l o we r t h re sho l d re g i s t e r . t h e a d c in p u t da t a is com p a r e d t o b o t h t h es e r e g i st ers. i f ad c i n p u t da ta i s la r g e r th a n t h e u p pe r thr e s h o l d r e gi s t e r , th en th e g a i n co n t r o l o u t p u t is decr em en ted b y 1. i f ad c in p u t da t a is sm al ler th a n t h e lo w e r th r e s h o l d r e gi s t er , th e n t h e g a in co n t r o l o u t p u t is i n cr em en t e d b y 1. w h en d e cr em en ti n g th e g a in co n t r o l o u t p u t , t h e chan g e is i mme dia t e . b u t when i n cr e m e n t i n g t h e o u t p u t , a d w e l l-tim e r e gist er is used t o dela y the c h a n ge . i f th e ad c in p u t is la rg er t h a n t h e u p p e r t h r e sh old r e g i st er val u e, t h e ga i n - co n t r o l o u t p u t is decr em en ted im m e dia t e l y t o p r ev en t o v er f l o w . w h en t h e ad c in p u t is lo w e r t h a n t h e lo w e r t h r e sh old r e g i st e r , a d w e l l t i m e r is lo ade d wi t h t h e val u e in t h e p r og ra mma b l e 20- b i t d w e l l- t i m e r e gis t e r . th e co u n t e r d e cr em en t s o n ce ev er y in p u t clo c k c y cle , as lo n g as t h e in p u t sig n a l r e ma in s b e lo w t h e l o we r t h re sho l d re g i ste r v a lu e. if t h e c o u n te r re a c he s 1 , t h e g a i n co n t r o l o u t p u t i s in cr e m e n t e d b y 1. i f t h e sig n al g o es a b o v e t h e l o we r t h re sho l d re g i ste r v a lu e, t h e g a i n a d ju st m e n t i s not m a d e , an d t h e nor m a l c o m p ar i s on to l o we r and upp e r t h re shol d r e g i st ers is ini t i a t e d on ce a g a i n. ther efo r e , t h e d w e l l t i mer p r o v ides t e m p oral h y st er esis and p r e v e n ts t h e g a in f r o m swi t c h in g con t in uo us l y . i n a typ i c a l a pplica t ion, if t h e a d c sig n a l go es b e lo w t h e lo w e r th r e s h o l d f o r a t i m e gr ea t e r th a n th e d w e l l tim e , th e n t h e g a in co n t r o l o u t p u t is in cr em en t e d b y 1. ga in co n t r o l b i ts co n t r o l t h e ga in ra n g i n g b l o c k, which a p p e a r s b e fo r e t h e a d c in t h e sig n a l c h a i n. w i t h each in cr em en t o f th e ga in co n t r o l o u t p u t , ga in in th e ga in - r a n gi n g b l oc k i s in cr eased b y 6.02 db . t h i s in cr ea se s t h e d y na mic ra n g e o f t h e i n p u t sig n al in t o t h e ad c b y 6.02 db . this ga in is com p en s a t e d fo r in the AD6636 b y r e lin e a r izing, as expla i n e d in t h e re li n e a r iz a t io n s e c t io n. th er efo r e , t h e a d 663 6 ca n in cr e a s e t h e d y na m i c ran g e o f th e ad c b y 42 db , p r o v ide d th a t t h e g a in - r a n gi n g b l ock ca n s u p p o r t i t . r e linea ri zation the ga i n in t h e ga in-ran g i n g b l o c k (ext er nal) is co m p e n s a t e d fo r b y r e lin e a r iz in g, usin g t h e ex p o n e n t b i ts exp[2:0] o f t h e in p u t p o r t . f o r this p u r p os e , t h e ga in co n t r o l b i t s a r e co nn e c t e d t o th e e x p[2:0] b i ts, p r o v iding an a t t e n u a t ion o f 6.02 db fo r e v er y in cr e a s e i n t h e ga in co n t rol o u t p u t . af t e r t h e ga i n i n t h e ext e r n al ga in-ran g i n g b l o c k and th e a t t e n u a t io n in t h e AD6636 (usin g ex p b i ts), th e sign al ga in is es sen t ial l y un c h an g e d . t h e o n ly cha n g e is t h e i n cr e a s e i n t h e d y na mic ra ng e o f t h e ad c. e x t e r n al ga in-r a n g i n g b l o c ks or ga in-ra n g i n g ad cs ha v e a d e la y a s socia t ed w i th c h a n g i n g th e g a in o f th e s i gn al . t y p i c a ll y , t h es e de l a ys can b e u p t o 14 clo c k c y cles. th e g a in chan g e i n t h e AD6636 (via e x p[2:0]) m u s t b e sy n c hr o n ize d wi t h t h e ga in cha n ge i n t h e gain-ran g i n g b l o c k (ext er na l). this is a l lo w e d in th e AD6636 b y p r o v idin g a f l exi b le de l a y , p r og ra m m a b l e 6 - b i t w o r d in t h e gai n co n t r o l r e g i ster . th e val u e in t h is 6-b i t w o r d g i v e s t h e de l a y i n in p u t clo c k c y cles. a p r og ra mma b l e p i p e l i ne
AD6636 rev. 0 | page 22 of 72 de l a y g i v e n b y t h e 6-b i t val u e ( m axim u m dela y o f 63 c l o c k c y cles) is place d b e tw e e n t h e ga i n co n t r o l o u t p u t a n d t h e exp[2:0] in p u t. ther efo r e , t h e e x t e r n al ga in-ra n g i n g b l o c k s s e t t ling dela ys ar e co m p en s a t e d fo r in th e ad6 636. n o t e tha t a n y ga i n c h a n g e s th a t a r e i n i t ia t e d d u ri n g th e r e lin e a r iza t io n p e r i o d a r e ig n o red . f o r exa m p l e , if th e AD6636 det e c t s t h a t a gain a d j u st m e n t is r e q u ir e d d u r i n g t h e r e li n e a r iz a - tio n p e r i o d o f a p r evio us ga in ad j u s t m e n t , th en th e n e w ad j u st m e n t is ig n o r e d . s e tting up the ga in c o nt rol b l ock t o s e t u p t h e gain co n t r o l b l o c k f o r in divid u al in p u t p o r t s, th e indivi d u a l u p p e r t h r e sh old r e g i sters an d lo w e r t h r e sh old r e g i st ers sh o u ld b e wr i t t e n wi t h a p p r o p r i a t e v a lues. th e 10- b i t val u es wr i t t e n i n t o u p p e r a n d l o w e r t h r e sh old r e g i st ers a r e co m p a r e d t o t h e 10 ms b b i ts of t h e a b s o l u t e ma g n i t ude calcula t ed u s i n g th e in p u t po r t da ta . t h e 20-b i t d w e l l tim e r r e g i st er sh o u ld ha v e t h e a p p r o p r i a t e n u m b er o f clo c k c y cles t o p r o v ide t e m p o r al h y st er esis. a 6-bi t r e li ne a r i z a t ion pi p e li n e del a y w o r d is s e t to sy n c hr o n i z e w i th th e s e t t l i n g d e la y i n th e e x t e rn a l g a i n r a n g i n g c i r c u i t r y . f i nal l y , th e ga in co n t r o l ena b le b i t is wr i t t e n wi th log i c 1 t o ac ti va t e t h e ga in co n t r o l b l o c k. on ena b l i ng, the ga in co n t r o l o u t p u t b i ts a r e m a de 000 (o u t p u t o n exp[2:0] p i n s ), which r e p r es en t t h e minim u m ga i n fo r t h e ext e r n al gain-ran g i n g cir c ui tr y a n d co r r es p o n d in g m i nim u m a t ten u a t io n d u r i n g r e lin e a r iz a t io n. the n o r m a l f u nc t i o n in g t a k e s ov er , as expla i ne d p r e v io usly in t h is s e c t io n. co m p l e x i n p u t s f o r co m p lex in p u ts (fo r m e d b y p a ir in g tw o i n pu t p o r t s), o n ly o n e s e t o f ex p[ 2:0] p i n s sh o u ld be use d as t h e ga in co n t r o l output . f o r t h e p a i r of i n put p o r t s a a n d b , g a i n c o n t ro l ci r c u i tr y f o r i n p u t p o r t a i s a c ti v e , a n d ex p a [2:0] s h o u ld be co nnec t e d ext e r n al l y as th e ga in co n t r o l o u t p u t . t h e ga in co n t r o l cir c ui tr y f o r i n p u t p o r t b is n o t ac t i va t e d (s h u t do wn), a n d exp b [2:0] is fo r c ed t o be e q ual t o exp[2:0 ] . 04998- 0- 025 dwell timer compare a < b inc dec exp gen from memory map exp [2:0] a b lower threshold register compare a > b from memory map b a lower threshold register from input ports increase external gain decrease external gain f i gur e 2 5 . ad66 36 ga i n c o nt r o l bl oc k di a g r a m adc i n pu t port m o ni t o r func ti on the AD6636 p r o v ides a p o w e r - m o ni t o r f u n c tion tha t can m o n i to r and ga t h er st a t ist i cs ab o u t t h e r e cei v e d sig n a l in a sign al c h a i n . e a c h in p u t p o r t is eq ui p p ed wi th an in di vid u al po w e r - m o n i t o r fu n c ti o n th a t ca n o p e r a t e bo th in r e al a n d in co m p lex m o des o f th e in p u t p o r t . t h is f u n c tio n b l o c k can o p era t e in one o f t h r e e m o des, which me asur e t h e fol l o w in g ove r a pro g r a mm abl e p e r i o d of t i m e : ? pe a k p o w e r ? me a n p o w e r ? n u m b er o f s a m p les cr os sin g a thr e s h o l d th e s e f u n c t i o n s a r e co n t r o l l e d v i a t h e 2 - b i t p o wer - m o ni t o r f u n c tio n s e lec t b i ts o f th e p o w e r m o ni t o r co n t ro l r e g i s t er f o r e a ch i n divid u al in p u t p o r t . th e in p u t p o r t s can be s e t fo r dif f er en t m o des , b u t o n ly on e f u n c t i on can b e ac t i v e a t a t i me fo r an y g i ven i n p u t p o r t . t h e t h re e mo d e s of op e r a t i o n c a n f u nc t i on c o n t i n u o u s l y ove r a p r o g r a mmabl e t i me p e r i o d . thi s t i me p e r i o d is p r o g r a mm e d as t h e n u m b er o f in p u t clo c k c y cles in a 24 -b i t ad c m o ni t o r p e r i o d r e gis t er ( a mp r). t h is r e gis t er is sep a ra te f o r eac h in p u t p o r t . an in t e r n a l ma g n i t ude st ora g e r e g i st er (m s r ) is us e d t o m o ni t o r , acc u m u la te , o r co un t, dep e n d in g o n th e m o de o f op e r a t i o n . p e a k d e te c t o r mo de ( c ontr ol bits 00) the ma g n i t ude o f t h e in p u t p o r t sig n al is m o ni to r e d o v er a p r og ra mma b l e t i me p e r i o d (g i v en b y ampr) to g i v e t h e p e ak va l u e det e c t e d . this m o de is s e t b y p r og ra mmin g l o g i c 0 in t h e po w e r - m o n i t o r fu n c ti o n se lect b i t s o f th e po w e r - m o n i t o r co n t r o l r e g i s t er f o r eac h individ u al in p u t p o r t . t h e 24-b i t a m p r m u s t be p r ogra m m e d bef o r e a c ti v a tin g th i s m o d e . af t e r ena b lin g t h is m o de , t h e v a l u e in t h e am p r is lo ade d i n to a monitor p e r i o d t i me r and t h e c o u n tdown i s s t ar te d. t h e ma g n i t ude o f t h e in p u t sig n al is co m p a r e d t o t h e ms r , and t h e gr ea t e r o f th e tw o i s u p da t e d ba c k in t o th e m s r . th e i n i t i a l val u e o f t h e msr is s e t t o t h e c u r r en t ad c i n pu t sig n al ma g n i t ude . this co m p a r is o n c o n t in ues un t i l t h e m o ni t o r p e r i o d t i mer r e ach e s a co un t o f 1. w h en t h e m o ni t o r p e r i o d t i m e r r e ach e s a co u n t o f 1, t h e val u e in t h e msr is t r a n sfer r e d t o t h e p o w e r - mo ni t o r h o lding r e g i st er , w h i c h c a n b e re a d t h rou g h t h e m i c r op or t or t h e s e r i a l p o r t . t h e m o ni t o r per i o d tim e r is r e lo ad ed wi th t h e val u e in t h e a m p r , an d t h e c o u n td ow n i s st ar te d. a l s o , t h e f i rst i n put s a m p l e s ma g n i t ude is u p da t e d i n t h e msr , a n d t h e com p a r is o n a n d u p da te p r o c e d ur e , as exp l a i n e d a b o v e , co n t in ues. i f th e in t e r r u p t is ena b le d , an i n t e r r u p t is gen e r a t e d , an d t h e in ter r u p t st a t us r e gis t er is u p da ted w h en t h e amp r r e ach e s a co un t o f 1.
AD6636 rev. 0 | page 23 of 72 f i gur e 26 is a b l o c k dia g ram o f th e p e ak det e c t o r logic. t h e ms r co n t a i ns t h e a b s o l u t e ma g n i t ude o f t h e p e ak dete c t e d b y th e p e ak det e c t o r log i c. power monitor holding register magnitude storage register compare a>b to memory map from memory map from input ports load clear load load 04998- 0- 026 is count = 1? down counter to interrupt controller power monitor period register f i g u re 26. a d c inp u t p e ak d e tec t or bl ock d i ag r a m mea n p o wer m o de ( c ontr ol bi ts 01) i n th i s m o de , th e m a gni t u d e o f th e in p u t po r t s i gn al i s in tegra t ed (b y ad d i n g a n acc u m u la t o r) o v er a p r ogra m m a b l e tim e p e r i o d (gi v en b y ampr) to gi v e th e in tegr a t e d ma gn i t ud e o f t h e in p u t sig n a l . this m o de is s e t b y p r og ra mmin g l o g i c 1 in th e po w e r m o ni t o r f u n c tio n se lect b i ts o f th e p o w e r m o n i t o r co n t r o l r e g i s t er f o r eac h individ u al in p u t p o r t . t h e 24-b i t amp r , r e p r es e n t i n g t h e p e r i o d o v er which i n t e g r a t ion is p e r f o r m e d , m u st be p r ogra m m e d b e f o r e ac ti va t i n g this m o d e . af t e r ena b lin g t h is m o de , t h e v a l u e in t h e am p r is lo ade d i n to a monitor p e r i o d t i me r , and t h e c o u n tdow n i s s t ar te d imm e di a t e l y . the 15-b i t ma g n i t ude o f in p u t sig n a l is r i g h t- s h if t e d b y n i n e b i ts t o gi v e 6-b i t da ta . this 6-b i t da ta is ad d e d t o t h e con t e n ts o f a 24-b i t h o ldi n g r e g i s t er , t h us p e r f o r min g a n a c cu m u la ti o n . t h e in t e gra t i o n co n t in u e s u n til th e m o ni t o r p e r i o d t i m e r r e ach e s a co un t o f 1. w h en t h e m o ni t o r p e r i o d t i m e r r e ach e s a co u n t o f 1, t h e val u e in t h e msr is t r a n sfer r e d t o t h e p o w e r - mo ni t o r h o lding r e g i st e r (a ft e r so m e f o rm a t ti n g ), wh i c h ca n be r e ad th r o u g h th e m i c r op or t or t h e s e r i a l p o r t . t h e mo n i tor p e r i o d t i me r i s r e l o a d e d w i th t h e v a l u e i n th e a m p r , a n d th e c o u n t d o w n i s s t a r t e d . als o , t h e f i rs t in pu t s a m p le sig n al ma g n i t ude is u p da t e d i n t h e m s r , a n d th e a c cum u la tio n co n t i n u e s w i th th e s u bs e q uen t in pu t s a m p les. i f t h e in ter r u p t is ena b le d , an i n te r r u p t i s ge ne r a te d, and t h e i n te r r u p t st a t u s re g i ste r i s u p da ted w h en t h e ampr r e ac hes a co un t o f 1. f i gur e 27 i l lu st r a te s t h e me an p o we r - mon i tor i ng l o g i c . the val u e i n t h e ms r is a f l o a t i n g -p o i n t n u m b er wi t h 4 ms bs a n d 20 ls bs. i f t h e 4 ms bs a r e e x p an d t h e 20 ls bs a r e ma g, t h e va l u e in dbfs ca n b e de co de d usin g t h e fol l o w in g e q u a t i o n : me a n p o w e r = 10 log ? ? ? ? ? ? ? ? ? ? ? ? ? ? ) 1 ( 20 2 2 exp mag 04998-0-027 power monitor holding register accumulator to memory map from memory map from input ports load clear load is count = 1? down counter to interrupt controller power monitor period register f i gure 27. adc inp u t mean p o wer - m o nitoring block d i ag r a m thresh ol d c r os sing mo d e ( c o n trol bits 1 0 ) i n t h is m o de o f o p era t ion, t h e ma g n i t ude o f t h e in p u t p o r t sig n al is m o ni t o r e d o v er a p r og ra mma b l e t i m e p e r i o d (g i v en b y amp r ) t o co u n t th e n u m b er o f tim e s i t cr os s e s a cer t a i n p r o g r a mmabl e t h r e shol d va l u e. this m o d e is s e t b y p r o g r a m- m i n g logic 1x (wher e x is a do n t c a r e b i t) in the p o w e r - m o ni t o r f u n c tio n se lect b i ts o f th e po w e r m o ni t o r co n t r o l r e gis t er f o r ea c h in di v i d u al i n p u t po r t . b e f o r e a c ti v a t i n g th is m o d e , th e u s e r n e e d s t o p r og ra m the 24-b i t amp r an d t h e 10-b i t u p p e r t h re sho l d re g i s t e r f o r e a ch i n d i v i d u a l i n put p o r t . t h e s a m e u p per th r e sh o l d r e gis t er is used f o r bo th po w e r m o ni t o r i n g an d g a i n co n t r o l (see th e a d c g a in c o n t r o l secti o n). af t e r en t e r i n g t h is m o de , t h e v a l u e in t h e am p r is lo ade d i n to a monitor p e r i o d t i me r , and t h e c o u n tdow n i s s t ar te d. t h e ma g n i t ude o f t h e in p u t sig n al is co m p a r e d t o u p p e r t h r e sh old reg i ster ( p ro g r amme d p r e v io u s ly ) o n e a ch i n p u t cl o c k c y cl e. i f th e in p u t s i gn al h a s m a gni t u d e gr ea t e r th a n t h e u p pe r th r e s h o l d r e g i st er , t h e n t h e ms r r e g i ster is in cr e m e n t e d b y 1. th e ini t ial va l u e o f t h e msr is s e t t o zer o . this com p a r is o n an d i n cr em e n t o f t h e ms r r e g i st er co n t in ues u n t i l t h e m o ni t o r p e r i o d t i m e r r e ach e s a co u n t o f 1. w h en t h e m o ni t o r p e r i o d t i m e r r e ach e s a co u n t o f 1, t h e val u e in t h e msr is t r a n sfer r e d t o t h e p o w e r m o ni t o r h o lding r e g i st er , w h i c h c a n b e re a d t h rou g h t h e m i c r op or t or t h e s e r i a l p o r t . t h e m o ni t o r per i o d tim e r is r e lo ad ed wi th t h e val u e in t h e amp r , a n d t h e co un t d o w n is st a r t e d . the ms r r e g i ster is als o cle a r e d t o a val u e o f zero . i f in t e r r u p ts a r e ena b le d , an i n t e r r u p t is ge ne r a te d, and t h e i n te r r u p t st a t u s re g i ste r i s u p d a te d w h e n t h e ampr r e ach e s a co un t o f 1. f i g u r e 28 i l l u st ra te s t h e t h r e sh old cr ossin g log i c. th e va l u e in t h e ms r is t h e n u m b er o f s a m p les t h a t ha v e an am pli t ude g r e a t e r t h a n t h e t h r e sh old r e g i st er . 04998-0-028 power monitor holding register compare a > b upper threshold register compare a > b to memory map from memory map from memory map from input ports load clear load is count = 1? down counter to interrupt controller power monitor period register b a f i gur e 2 8 . adc inp u t thr e shol d cr o ssing blo c k d i a g r a m
AD6636 rev. 0 | page 24 of 72 a dditi onal con t rol bits f o r addi t i o n al f l exi b i l i t y i n t h e p o w e r m o ni t o r i n g p r o c ess, tw o c o n t ro l bit s are prov i d e d i n t h e p o we r - mon i tor c o n t ro l re g i ste r . the tw o con t r o l b i t s a r e t h e dis a b l e m o ni t o r p e r i o d t i m e r b i t a n d t h e cle a r - on-r e a d b i t. th es e o p t i o n s ha v e t h e s a me f u n c t i on i n a l l t h re e mo d e s of op e r a t i o n . disa bl e m o nit o r p e ri o d t i me r b i t w h en t h e dis a ble m o ni t o r p e r i o d t i m e r b i t is wr i t t e n wi t h l o g i c 1, t h e t i mer co n t in ues t o r u n b u t do es n o t ca us e t h e co n t e n ts o f t h e ms r t o b e t r a n s f er r e d t o t h e h o ldin g r e g i st er when t h e co u n t r e ach e s 1. this f u n c t i on o f t r a n sferr i n g t h e ms r t o t h e p o wer m o ni t o r h o ldin g r e g i st er and r e s e t t in g t h e m s r i s now c o n t ro l l e d by a re a d op e r at i o n o n t h e m i c r op or t or se ri al po r t . w h e n a m i c r op or t or s e r i a l p o r t re a d i s p e r f or me d on t h e p o w e r m o ni t o r h o lding r e g i st er , t h e msr val u e is t r a n sfer r e d t o t h e h o ldi n g r e g i st er . af t e r t h e r e ad o p er a t io n, t h e t i m e r is r e loa d ed w i t h th e a m p r v a l u e . i f th e tim e r r e ac h e s 1 be f o r e th e m i c r op or t or s e r i a l p o r t re a d , t h e m s r v a lu e i s not t r a n s f e r re d t o t h e h o ldi n g r e g i st er , as i n n o r m al o p era t ion. the t i m e r st i l l g e n e r a t e s an in ter r u p t o n th e AD6636 in ter r u p t p i n and u p da tes t h e i n t e r r u p t st a t us r e g i st er . an i n t e r r u p t a p p e a r s o n t h e irp p i n, if in t e r r u p ts a r e ena b le d in t h e i n t e r r u p t ena b le r e g i st er . c l ea r - o n - r ead b i t this co n t r o l b i t is valid o n ly w h en t h e dis a b l e m o ni t o r p e r i o d t i mer b i t is l o g i c 1. w h e n b o t h o f t h es e b i ts a r e s e t, a r e ad o p era t ion t o ei t h er t h e micr o p or t o r t h e s e r i al p o r t r e ads t h e m s r v a l u e a n d th e m o ni t o r pe r i od tim e r i s r e loa d ed wi th t h e amp r va l u e . th e m s r is cle a re d (wr i t t en wi t h c u r r en t in p u t s i gn al m a gni t u d e i n p e ak po w e r a n d m e a n po w e r m o de ; w r i t t e n wi t h a zer o in t h r e sh old cr o s si n g mo de) , an d n o r m a l o p er a t i o n co n t in ues. w h en t h e m o ni t o r p e r i o d t i m e r is dis a b l e d an d t h e cle a r - o n - r e ad b i t is s e t, a r e ad o p era t io n to t h e p o w e r m o ni to r h o ldin g r e g i st er cle a rs t h e con t e n ts o f t h e m s r and , t h er efo r e , t h e p o w e r mon i tor l o op re st ar t s . i f t h e cle a r - on-re a d b i t is l o g i c 0, t h e r e ad op era t io n t o t h e m i c r op or t or s e r i a l p o r t d o e s n o t c l e a r t h e m s r v a lu e af te r it i s t r a n sfer r e d in t o t h e h o lding r e g i st er . the val u e f r o m t h e pre v i o u s mon i t o r t i me p e r i o d p e r s i s t s , an d it c o n t i n u e s to b e c o mp a r e d , a c c u mu l a t e d , o r i n c r e m e n t e d , b a s e d o n n e w i n p u t s i gn al m a gni t u d e v a l u e s . qu adr a tu re i/q c o rrec tion bl o c k w h en t h e i and q p a t h s a r e dig i t i ze d usin g s e p a ra t e ad cs, as i n q u adr a t u r e if d o wn-con versio n , a misma t ch o f ten o c c u rs betw een i an d q d u e t o va r i a t io n s in t h e ad cs f r o m th e m a n u fac t ur in g p r o c es s. th e AD6636 is eq ui p p ed wi th tw o q u adr a t u r e co r r ec tio n b l o c ks tha t c a n be use d to co r r ec t i/q misma t ch er r o rs in a com p lex b a s e b a n d in pu t st r e a m . th es e i / q misma t ch es can r e s u l t in sp ec t r al dis t o r t i o n s, and r e m o vin g th em i s u s e f ul . t w o such b l o c ks a r e p r es en t, one e a ch fo r t h e i / q sig n al fo r m e d b y co m b ini n g t h e a and b in p u ts an d t h e c and d i n p u ts, r e sp e c t i v e ly . the i/q co r r e c t i o n b l o c k c a n b e ena b le d w h en t h e p o r t a (o r p o r t c) co m p lex da t a ac ti v e b i t is ena b led in t h e a d c i n put c o n t ro l re g i ste r . t h i s bl o c k i s by p a ss e d w h e n re a l in p u t da t a is p r e s en t on t h e ad c in p u t p o r t s, b e ca us e t h er e is n o p o s s ib il i t y o f i/q m i sm a t c h in r e al da t a . t h e i / q or qu a d r a tu re c o r r e c t i on bl o c k c o ns i s t s of t h re e indep e n d en t sub b l o c ks: dc co r r e c t i o n , phas e cor r e c t i o n , a n d a m pli t ude co r r e c t i o n . thr e e indi vi d u al b i ts i n t h e ab (o r cd) co r r ec tio n co n t r o l r e g i s t ers ca n be us e d t o ena b le o r dis a b l e e a ch o f t h es e sub b l o c ks i n de p e n d e n t l y . f i gur e 29 sh o w s t h e co n t e n ts and de f i ni t i o n s o f t h e r e g i st ers r e l a t e d t o t h e q u a d ra t u r e c o rr ecti o n b l oc k . dc estimate dc estimate magnitude error estimation phase estimate [13:0] phase estimate [13:0] q_out [15:0] to next block i_out [15:0] to next block i [15:0] from input port q [15:0] from input port 04998- 0- 029 phase error estimation magnitude estimate [13:0] f i g u re 29. q u ad r a t u r e cor r e c t io n b l o c k d i ag r a m
AD6636 rev. 0 | page 25 of 72 table 11. correction control registers register bits decription i/q correction control 15C12 amplitude loop bw 11C8 phase loop bw 7C4 dc loop bw 3 reserved (logic 0) 2 amplitude correction enable 1 phase correction enable 0 dc correction enable dc offset correction i 31C16 dc offset q dc offset correction q 15C0 dc offset i amplitude offset correction 31C16 amplitude correction phase offset correction 15C0 phase correction dc correction all adcs have a nominal dc offset related to them. if the adcs in the i and q path have different dc offsets due to variations in manufacturing process, the dc correction circuit can be used to compensate for these dc offsets. writing logic 1 into the dc correction enable bit of the ab (or cd) correction control register enables the dc correction block. two dc estimation blocks are used, one each for the i and q paths. the estimated dc value is subtracted from the i and q paths. therefore, the dc signal is removed independently from the i and q path signals. a cascade of two low-pass decimating filters estimates the dc offset in the feedback loop. a decimating first-order cic filter is followed by an interpolating second-order cic filter. the decimation and interpolation values of the cic filters are the same and are programmable between 2 12 and 2 24 in powers of 2. the 4-bit dc loop bw word in the i/q correction control ab (or cd) register is used to program this decimation (interpolation) value. when the dc loop bw is a 0, decimation is 2 12 , and when the dc loop bw is 11, decimation is 2 24 . when the dc correction circuit is enabled, the dc correction values are estimated. the values, which are estimated independ- ently in the i and q paths, are subtracted independently from their respective datapaths. these dc correction values are also available for output continuously through the dc correction i and dc correction q registers. these registers contain register 16-bit dc offset values whose msb-justified values are subtracted directly from msb-justified adc inputs for the i and q paths. when the dc correction circuit is disabled, the value in the dc correction register is used for continuously subtracting the dc offset from i and q datapaths. this method can be used to manually set the dc offset instead of using the automatic dc correction circuit. phase correction when using complex adc input, the i and q datapaths typically have phase offset, caused mainly by the local oscillator and demodulator ic. the AD6636 phase-offset correction circuit can be used to compensate for this phase offset. when the phase correction enable bit is logic 1, the phase error between i and q is estimated (ideally, the phase should be 90). the phase mismatch is estimated over a period of time determined by the integrator loop bandwidth. this integrator is implemented as a first-order cic decimating filter, whose decimation value can vary between 2 12 and 2 24 in powers of 2. phase loop bw (bits [11:8]) of the i/q correction control register determine this decimation value. when phase loop bw equals 0, the decimation value is 2 12 , and when phase loop bw is 11, the decimation value is 2 24 . while the phase offset correction circuit is enabled, the tan(phase_mismatch) is estimated continuously. this value is multiplied with q path data and added to i path data continuously. the estimated value is also updated in the phase offset correction register. the tan(phase_mismatch) can be 0.125 with a 14-bit resolution. this converts to a phase mismatch of about 7.125. when the phase offset correction circuit is disabled, the value in the phase correction register multiplied with the q path data and added to the i path data continuously. this method can be used to manually set the phase offset instead of using the automatic phase offset correction circuit. amplitude correction when using complex adc input, the i and q datapaths typically have amplitude offset, caused mainly by the local oscillator and the demodulator ic. the AD6636 amplitude offset correction circuit can be used to compensate for this amplitude offset. when the amplitude correction enable bit is logic 1, the amplitude error between the i and q datapaths is estimated. the amplitude mismatch is estimated over a period of time determined by the integrator loop bandwidth. this integrator is implemented as a first-order cic decimating filter, whose decimation value can vary between 2 12 and 2 24 in powers of 2. phase loop bw (bits [11:8]) of the i/q correction control register determines this decimation value. when the phase loop bw equals 0, the decimation value is 2 12 , and when phase loop bw is 11, the decimation value is 2 24 . while the amplitude offset correction circuit is enabled, the difference (mag(q) C mag(i)) is estimated continuously. this value is multiplied with the q path data and added to the q path data continuously. the estimated value is also updated in the phase offset correction register. the difference (mag(q) C mag(i)) can be between 1.125 and 0.875 with a 14-bit resolution.
AD6636 rev. 0 | page 26 of 72 the am pli t ude o f t h e si n e and cosin e a r e r e p r e s en te d usin g 17 b i ts. th e w o rs t - cas e s p ur io us sig n al f r o m t h e nco is b e t t e r tha n ?100 db c fo r al l o u t p u t f r e q uen c ies. w h en am pli t ude o f fs et co r r e c t i o n cir c ui t is dis a b l e d , t h e val u e in t h e am pli t ude o f fs et co r r e c t i o n r e g i st er m u l t i p lie d wi t h t h e q p a t h da t a and adde d to q p a t h d a t a co n t in uously . this m e t h o d can b e us e d t o man u al ly s e t t h e am pl i t ude o f fs et in st e a d o f usin g t h e a u t o ma t i c am pli t ude o f fs et co r r e c t i o n cir c ui t. b e ca us e al l the f i l t er in g in t h e AD6636 is lo w-p a s s f i l t er ing, th e ca r r i er o f in t e r e s t is t u n e d do wn t o dc (f r e q u enc y = 0 h z ). t h is is il l u s t ra t e d in f i gur e 30. on ce th e signal o f in ter e s t is t u n e d do wn t o dc, th e un wan t ed ad jac e n t c a r r i er s ca n be r e jec t e d usin g t h e lo w-p a s s f i l t er in g t h a t fol l o w s. inpu t cros sbar ma trix the AD6636 has fo ur ad c in p u t p o r t s an d six c h a n n e ls. t w o in p u t p o r t s can b e p a ir e d t o supp o r t co m p lex in p u t p o r t s. cr os sba r m u x s e lec t io n al lo ws eac h c h a n ne l t o s e lec t i t s in p u t sig n al f r o m t h e fol l o w in g s o ur c e s: fo ur r e al in p u t p o r t s, tw o co m p lex in p u t p o r t s, a n d in ter n a l ly gen e r a te d ps eudo r a n d om s e q u e n ce (r efer r e d t o as a pn s e q u en c e , which c a n b e e i t h er r e al or c o m p l e x ) . e a ch ch an n e l h a s an i n put c r o s s b ar ma t r i x to s e l e c t f r om t h e ab ove - l i st e d i n put s i g n a l c h oi c e s . nc o f r e q uenc y the nc o f r e q uen c y val u e is g i v e n b y t h e 32 -b i t tw os co m p le m e n t n u m b er en t e r e d in t h e n c o f r e q u e n c y r e g i st er . f r e q uen c ies b e t w e e n ?cl k /2 and cl k/2 (cl k /2 excl ude d ) a r e r e p r es en t e d usin g t h is f r e q uen c y w o r d : 0x8000 0000 r e p r es en ts a f r eq uen c y g i v e n b y ?clk/2 . 0x0000 0000 r e p r es en ts dc (f r e q u en c y is 0 h z ). the s e le c t ion o f t h e i n p u t sig n a l fo r a p a r t ic u l a r cha n n e l is made usin g a 3 - b i t cr ossb a r m u x s e le c t w o r d and a 1- b i t co m p lex da t a in p u t b i t s e le c t io n in t h e ad c i n pu t co n t r o l r e g i ster . e a ch ch a nnel has a s e p a r a te s e le c t io n for in d i v i d u a l co n t r o l. t a b l e 1 2 lists t h e valid co m b ina t io ns of t h e cr ossb a r m u x se lect w o r d , th e co m p le x da ta i n p u t b i t val u e s , a n d th e co r r esp o n d in g i n p u t sig n a l s e le c t io n s . 0x7fff f fff r e p r esen ts clk/2 ? clk / 2 32 . the nco f r e q uen c y w o r d c a n be calc u l a t e d us in g fol l o w in g t h e eq ua ti o n : ( ) cl k clk ch f f f freq nco , mod 2 = _ 32 numeric a ll y c o ntrol l ed oscill a t or (nc o ) wher e: e a ch chan nel c o ns ists o f an i n dep e nde n t c o m p l e x nc o and a co m p lex mixer . this p r o c essi n g st a g e com p r i s e s a dig i t a l t u n e r co n s ist i n g o f t h r e e m u l t i p li ers a n d a 32- b i t com p lex n c o . the n c o s e r v es as a q u a d ra t u r e lo ca l os ci l l a t o r c a p a b l e o f p r o d uc- in g a n n c o f r e q uen c y o f b e twe e n ?cl k /2 and +clk/2 wi t h a re s o lut i on of c l k / 2 32 i n com p lex m o de , w h er e clk is t h e i n p u t cl o c k f r e q u e nc y . nc o _ f r e q is t h e 32- b i t tw os co m p le m e n t n u m b er r e p r es en t - in g t h e nco f r e q uen c y r e g i s t e r . f ch is t h e desir e d ca r r i er f r e q uen c y . f cl k is th e c l o c k ra t e f o r th e c h a n n e l un d e r co n s id era t io n . m o d( ) is a r e ma inder f u n c t i o n . f o r exa m p l e , m o d(110, 100) = 10 a n d , fo r n e g a ti v e n u m b ers, m o d(?32, 10) = ? 2 . t h e f r e q u e nc y word u s e d f o r ge ne r a t i ng t h e n c o i s a 3 2 - bit word. th i s wor d i s u s e d to ge n e r a te a 2 0 - b i t p h a s e word. a 16-b i t phas e o f fs et w o r d is ad de d to t h is phas e w o r d . 18 b i ts o f t h is phas e w o r d a r e us e d t o g e nera t e t h e si n e and cosine o f t h e r e q u i r ed n c o f r eq u e n c y . n o t e t h a t t h is e q ua t i o n a p p l ies t o t h e al iasin g of sig n als in t h e d i gi t a l d o m a in (th a t i s , alia si n g in tr o d uced w h en d i g i tiz i n g a n alog si gn als). ta ble 12. cros s b a r mux select i o n for cha n ne l input si gna l complex input bit crossbar mux s e lect bit input signal se lection 0 000 input port a ma gnitude and ex ponent pins drive the channe l. 0 001 input port b magnitude and ex ponent pins drive the channe l. 0 010 input port c ma gnitude and ex ponent pins drive the channe l. 0 011 input port d ma gnitude and ex ponent pins drive the channe l. 0 100 internal pn sequences magnit ude and expone n t bits drive the channe l. 1 0 0 0 input ports a and b form a pair to drive i and q paths of the channel, respectively . input port a exponent pins drive the c h anne l exp o nen t bits. 1 0 0 1 input ports c and d form a pair t o drive i an d q paths of the channel, respectively . input port c exponent pins drive the c h anne l exp o nen t bits. 1 010 internal pn sequences magnit ude and expone n t bits drive the channe l.
AD6636 rev. 0 | page 27 of 72 04998-0-030 nco tunes signal to signal of interest after frequency translation signal of interest signal of interest image signal of interest image ? fs/2 ? 7fs/8 ?3fs/8 ?5fs/16 ? fs/4 ? 3fs/16 ?fs/8 ? fs/16 dc fs/16 fs/8 3fs/16 fs/4 5fs/16 3fs/8 7fs/8 fs/2 ?fs/2 ?7fs/8 ?3fs/8 ? 5fs/16 ?fs/4 ?3fs/16 ? fs/8 ?fs/16 dc fs/16 fs/8 3fs/16 fs/4 5fs/16 3fs/8 7fs/8 fs/2 frequency translation (single 1mhz channel tuned to baseband) wideband input spectrum (30mhz from high speed adc) wideband input spectrum (?fsamp/2 to fsamp/2) f i gure 30. f r equen c y t r a n slat io n p r in cipl e using th e nc o and m i x e r f o r exa m p l e , if th e ca r r i er f r eq u e n c y is 100 mh z an d t h e c l o c k f r eq uen c y is 80 mh z, ( ) 25 . 0 = 80 20 = , mod cl k clk ch f f f this, in t u r n , con v er ts t o 0x400 0 0000 in the 32 -b i t tw os co m p le m e n t r e p r es en t a t i o n fo r nc o _ f r e q . i f t h e c a r r i er f r eq uen c y is 50 m h z and t h e clo c k f r e q uen c y is 80 mh z, ( ) 125 . 0 = 80 10 = , mod cl k clk ch f f f this, in t u r n , con v er ts t o 0x e000 0000 in the twos co m p lem e n t 32-b i t r e p r es en t a tio n . mix e r the nc o is acc o m p a n ie d b y a mixer . i t s o p era t io n is simi la r t o a n a n alog m i x e r . i t do es th e do wn-co n v e r s io n o f in p u t signals (r eal o r co m p lex) b y u s in g th e n c o f r eq uen c y as a lo cal oscilla t o r . f o r r e al i n p u t si gn als, th i s m i x e r perf o r m s a r e al mixer o p era t io n (wi t h tw o m u l t i p liers). f o r co m p lex in p u t sign als, th e m i xer per f o r m s a co m p lex m i x e r o p era t io n (wi t h fo ur m u l t i p liers). th e mixer ad j u s t s i t s o p era t io n bas e d on t h e i n p u t si gn al (r eal o r co m p le x) p r o v i d ed t o ea ch in d i v i d u al chan nel. bypass the nc o and t h e m i xer can b e b y p a ss e d i n divi d u a l ly in e a ch c h a n n e l by w r it i n g l o g i c 1 i n t h e nc o by p a s s b i t i n t h e n c o co n t r o l r e g i st er o f t h e cha n ne l u n der con s idera t io n. w h en b y p a s s ed , down-co n versio n is no t p e r f o r m e d and the AD6636 c h a n n e l f u n c tio n s sim p l y as a r e al f i l t er o n co m p lex da ta . t h is is us ef u l fo r b a s e b a nd s a m p lin g a p plica t io n s , in w h ich t h e in p u t p o r t a (o r c) is co nnec t e d t o t h e i signal p a th wi t h in t h e f i l t er a n d t h e i n p u t p o r t b (o r d) is c o nn ec t e d t o the q signal p a th. this mig h t b e desir e d , if t h e dig i t i ze d sig n a l has a l r e ad y b e e n co n v er t e d t o baseba nd in p r io r a n alog s t a g es o r b y o t h e r digi tal pre p ro c e s s i n g . clea r phase a c cum u lato r on hop w h en c l ea r n c o accum u la t o r b i t o f n c o co n t r o l r e gis t er is set (l og ic 1), t h e nc o phas e acc u m u l a t o r is cle a r e d p r io r t o a f r e q u e nc y hop . r e f e r to t h e c h ip s y nch r on i z a t i o n s e c t i o n f o r det a ils o n f r eq u e n c y h o p p i ng. this en s u r e s a con s is t e n t p h as e of t h e n c o on e a ch h o p . th e nc o phas e o f fs et i s una f fe c t e d b y t h is s e t t in g and is st i l l in ef fe c t . i f phas e-con t i n uo us h o p p i n g is n e ed ed , t h i s b i t s h o u l d be c l e a r e d ( n co a c cu m u l a t o r i s n o t cle a r e d). the last phas e i n t h e nc o phas e r e g i ster is t h e i n i t ia ti n g po in t f o r th e n e w f r eq ue n c y . phase dithe r the AD6636 p r o v ides a p h as e di t h er o p tion fo r im p r o v in g t h e sp ur io us p e r f o r ma nce o f t h e nc o . w r i t in g l o g i c 1 in t h e phas e di t h er ena b le b i t o f n c o con t r o l r e g i st er o f individ u al cha n nels ena b les phas e di t h er . w h en phas e di t h er is enable d , ra n d om phas e is ad de d to ls bs o f t h e phas e acc u m u l a to r o f t h e n c o . w h en phas e di t h er is enab le d , sp urs d u e t o phas e t r un c a t i on in t h e n c o a r e ran d omi z e d . the e n erg y f r o m t h e s e sp urs is sp r e ad i n t o t h e n o is e f l o o r an d t h e sp ur io us f r ee d y namic ra n g e is in cr e a s e d a t t h e exp e n s e o f a v e r y slig h t de cre a s e i n t h e snr . the ch o i ce o f whet her t o us e phas e d i t h er in a sy ste m is u l t i ma tely de cide d b y t h e sy ste m g o als. i f lo w e r s p urs a r e desir e d a t t h e exp e ns e o f a slig h t ly ra is e d n o is e f l o o r , phas e di t h er sh o u ld b e em pl o y e d . i f a lo w n o is e f l o o r is de sir e d an d t h e hi g h er sp urs c a n b e toler a te d o r f i l t e r ed b y s u bs eq u e n t s t a g e s , t h en p h a s e d i t h er i s n o t n e e d ed .
AD6636 rev. 0 | page 28 of 72 a m plitude dit h er am p l i t ude di t h er ca n be us e d to im p r o v e s p ur io us p e r f o r ma n c e o f t h e nc o . am pli t ude di t h er is ena b le d b y wr i t in g l o g i c 1 i n t h e am pli t ude di t h er ena b le b i t o f t h e nc o co n t r o l r e g i st er o f t h e ch a n nel u n d e r c o ns i d e r a t i o n . r a nd o m am p l itu d e i s a d d e d t o t h e l s bs o f t h e si n e an d cosi n e am pl i t udes, when t h is fe a t ure is ena b le d . am pli t ude di t h er i m p r o v es p e r f o r m a n c e b y ra n d omi z in g t h e a m pl i t ude q u an t i za t i on er r o rs wi t h in t h e ang u l a r - to - c ar t e s i an c o n v e r s i on of t h e nc o . th i s opt i on mig h t r e d u ce spurs a t t h e exp e ns e o f a slig h t ly r a is e d n o is e f l o o r . am pli t ude di t h er and phas e di t h er can b e us e d t o g e t h er , s e p a ra te ly , o r n o t a t al l. nc o f r e q uenc y hold- o ff r e g i ster w h en t h e n c o f r e q uen c y r e g i st ers a r e wr i t t e n b y t h e m i c r op or t or s e r i a l p o r t , d a t a i s p a ss e d to a sh a d ow re g i ste r . da t a can b e m o v e d t o t h e main r e g i st ers w h e n t h e chann e l c o me s out of sl e e p mo d e , or w h e n a s y nc hop o c c u r s . i n e i t h e r ev en t, a co u n t e r ca n be lo ade d wi t h t h e nco f r eq uen c y h o l d - o f f r e g i st er val u e . the 16- b i t unsig n e d i n t e g e r c o un t e r st a r ts co u n ti n g d o wn , c l oc k e d b y th e in p u t po r t c l oc k se lect e d a t th e cr ossb a r m u x. w h en t h e co u n ter r e ach e s 0, t h e ne w f r e q ue n c y val u e in t h e shado w r e g i st er is wr i t t e n t o t h e nc o f r e q uen c y r e g i st er . w r i t ing 1 in t h is h o ld-of f r e g i st er u p da tes t h e n c o f r eq uen c y r e gis t er as so o n as the s t a r t sy n c o r ho p syn c o c c u r s . s e e t h e c h i p s y n c hr o n iz a t ion s e c t io n fo r det a i l s. phase o ffset the phas e o f fs et r e g i st er can b e wr i t t e n wi t h a val u e t h a t is adde d as an o f fs et t o t h e phas e acc u m u l a t o r o f t h e n c o . this 16-b i t r e g i s t er is in t e r p r e t e d as a 16-b i t un sig n e d in t e g e r . a 0x0000 in this r e g i s t er co r r es p o n d s t o a 0 radian o f fs et a n d a 0xffff co r r es po n d s t o an o f fset o f 2 (1 ? 1/ 2 16 ) rad i a n s. t h is r e gis t er al l o ws m u l t i p le n c o s (m ul t i p l e cha n n e ls) t o b e syn c hr o n ize d t o p r o d uce com p lex sin u s o ids wi t h a k n o w n and st e a d y phas e dif f er en ce . hop s y nc a h o p sy n c sh o u ld be iss u ed t o th e c h ann e l , w h en t h e c h a n ne l s n c o f r eq u e n c y n eeds t o b e c h a n g e d f r o m o n e f r eq u e n c y t o a dif f er en t f r e q uen c y . this fe a t ure is dis c uss e d in det a i l i n t h e c h i p s y n c hr o n i z a t ion s e c t ion. fifth- orde r cic fil t er the sig n al p r o c essin g st a g e i m m e di a t e l y a f t e r t h e n c o is a cic f i l t er st a g e . this st a g e im ple m e n ts a f i xe d-co ef f i cien t, decima ting, cas c ade in teg r a t ed co m b f i l t er . th e in p u t r a t e t o this f i l t er is t h e s a me as t h e da t a ra te a t t h e i n p u t p o r t ; t h e o u t p u t r a te f r om t h i s s t age i s d e p e nd e n t on t h e d e c i m a t i on f a c t or . cic in cic m f f = t h e d e cim a ti o n ra ti o , m ci c , ca n be p r og ra mm e d f r o m 2 t o 32 (o nly in t e ger val u es). th e 5- b i t w o r d in t h e cic de cima t i on r e gis t er is used to set th e ci c de cim a tio n fac t o r . a b i na r y val u e of one l e ss t h a n t h e d e c i m a t i on f a c t or i s w r itte n i n to t h i s r e gis t er . t h e de cim a tio n ra tio o f 1 ca n be ac hie v ed b y b y p a s s ing t h e c i c f i l t er st a g e . th e f r e q ue n c y r e sp o n s e o f t h e f i l t er is g i v e n b y t h e fol l o w in g e q u a t i o n s. t h e ga in and p a ss- b a n d dr o o p o f th e ci c s h o u ld be calcula t ed b y th e s e e q ua ti o n s. b o th pa ra m e - t e r s ca n b e o f fset in t h e rcf s t ag e . 5 1 ) 5 ( 1 1 2 1 ) ( ? ? ? ? ? ? ? ? ? ? = ? ? + 5 ) 5 ( sin sin 2 1 ) ( ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = + w h er e: f in is t h e da t a i n p u t ra te t o t h e cha n n e l u n der c o n s idera t ion. s cic , t h e s c a l e f a c t o r , i s a p r o g r a m m a b l e u n s i g n e d i n t e g e r betw een 0 an d 20. the a t t e n u a t ion o f t h e da t a i n t o t h e c i c s t a g e sh o u ld b e co n t r o l l ed in 6 db in cr em en ts. f o r th e best d y na mic ra n g e , s ci c shou l d b e s e t to t h e s m a l l e st va lu e p o ss ibl e ( l owe s t a t te n u a t ion p o ssi b le) wi t h ou t cr e a t i ng a n over f l o w co n d i t i o n. this c a n b e acco m p lish e d s a fe l y usin g t h e fol l o w in g e q u a t i o n , w h er e input _ le v e l i s t h e la r g e s t pos s i b le f r a c ti o n o f th e full- s cale v a l u e a t t h e i n p u t p o r t . this val u e is ou t p ut f r o m t h e n c o st a g e an d p i p e li n e d in t o t h e c i c f i l t er . ( ) ( ) 5 _ 5 2 log - level input ci c m ceil ci c s = ( ) _ 2 5 5 = + bypass the f i f t h-o r der ci c f i l t er c a n b e b y p a s s e d w h e n n o de cima t i on is r e q u ir e d o f i t . w h en i t is b y p a ss e d , t h e s c a l in g o p era t ion is n o t p e r f o r m e d . i n b y p a s s m o de , t h e o u t p ut o f t h e c i c f i l t er is t h e s a me as t h e in p u t o f t h e c i c f i l t er . cic r e je c t ion t a b l e 13 i l l u st ra tes t h e am o u n t o f b a n d w i d t h as a p e r c en t a ge o f th e da ta ra t e i n t o th e c i c s t a g e , wh i c h ca n b e p r o t ect e d wi th va r i o u s de cima t i o n ra t e s an d a l i a s r e j e c t io n sp e c if ica t ion s . th e maxim u m in p u t ra t e in t o t h e ci c is 150 mh z (th e s a me as t h e maxim u m in p u t p o r t da ta r a t e ). the da t a ma y b e s c ale d t o an y o t h e r al lo wa b l e s a m p le ra t e .
AD6636 rev. 0 | page 29 of 72 t a b l e 13 can be us ed t o decide t h e minim u m de cima tion r e q u ir e d i n t h e ci c s t a g e t o p r e s er v e a cer t a i n b a ndwi d t h. th e ci c5 s t a g e ca n p r o t e c t a m u ch wider b a n d wi d t h t o an y g i v e n r e jecti o n , w h en a d e ci ma ti o n ra ti o lo w e r th a n th a t i d en ti f i e d in t h e t a b l e is us e d . th e t a b l e h e l p s t o calc u l a t e an u p p e r b o u n da r y o n decima tion, m ci c , g i ven t h e desir e d f i l t er ch a r ac ter i st ics. table 13. ssb cic5 alias rejection table (f in = 1) mcic5 ?60 db ?70 db ? 80 db ?90 db ?100 db 2 8 . 0 7 8 6 . 3 9 3 5 . 0 6 6 4 . 0 0 8 3 . 1 8 3 3 6 . 3 6 7 5 . 1 1 4 . 1 0 7 3 . 2 9 7 2 . 6 4 2 4 5 . 0 2 2 4 . 0 5 7 3 . 2 7 1 2 . 6 3 6 2 . 1 2 1 5 4 . 1 0 7 3 . 3 2 6 2 . 6 8 7 2 . 1 7 1 . 7 4 8 6 3 . 4 6 3 2 . 8 0 8 2 . 2 7 1 . 8 3 6 1 . 4 8 7 2 . 9 8 9 2 . 4 2 5 1 . 9 6 2 1 . 5 8 8 1 . 2 8 1 8 2 . 6 2 7 2 . 1 3 3 1 . 7 2 6 1 . 3 9 7 1 . 1 2 8 9 2 . 3 4 2 1 . 9 0 2 1 . 5 4 1 . 2 4 7 1 . 0 0 7 1 0 2 . 1 1 3 1 . 7 1 6 1 . 3 9 1 . 1 2 5 0 . 9 0 9 1 1 1 . 9 2 4 1 . 5 6 3 1 . 2 6 6 1 . 0 2 5 0 . 8 2 8 1 2 1 . 7 6 5 1 . 4 3 5 1 . 1 6 2 0 . 9 4 1 0 . 7 6 1 3 1 . 6 3 1 1 . 3 2 6 1 . 0 7 4 0 . 8 7 0 . 7 0 3 1 4 1 . 5 1 6 1 . 2 3 2 0 . 9 9 8 0 . 8 0 9 0 . 6 5 3 1 5 1 . 4 1 6 1 . 1 5 1 0 . 9 3 2 0 . 7 5 5 0 . 6 1 1 6 1 . 3 2 8 1 . 0 7 9 0 . 8 7 4 0 . 7 0 8 0 . 5 7 2 1 7 1 . 2 5 1 . 0 1 6 0 . 8 2 3 0 . 6 6 7 0 . 5 3 9 1 8 1 . 1 8 1 0 . 9 6 0 . 7 7 8 0 . 6 3 0 . 5 0 9 1 9 1 . 1 1 9 0 . 9 1 0 . 7 3 7 0 . 5 9 7 0 . 4 8 3 2 0 1 . 0 6 4 0 . 8 6 5 0 . 7 0 1 0 . 5 6 8 0 . 4 5 9 2 1 1 . 0 1 3 0 . 8 2 4 0 . 6 6 7 0 . 5 4 1 0 . 4 3 7 2 2 0 . 9 6 7 0 . 7 8 6 0 . 6 3 7 0 . 5 1 6 0 . 4 1 7 2 3 0 . 9 2 5 0 . 7 5 2 0 . 6 1 0 . 4 9 4 0 . 3 9 9 2 4 0 . 8 8 7 0 . 7 2 1 0 . 5 8 4 0 . 4 7 4 0 . 3 8 3 2 5 0 . 8 5 2 0 . 6 9 2 0 . 5 6 1 0 . 4 5 5 0 . 3 6 7 2 6 0 . 8 1 9 0 . 6 6 6 0 . 5 4 0 . 4 3 7 0 . 3 5 3 2 7 0 . 7 8 9 0 . 6 4 1 0 . 5 2 0 . 4 2 1 0 . 3 4 2 8 0 . 7 6 1 0 . 6 1 8 0 . 5 0 1 0 . 4 0 6 0 . 3 2 8 2 9 0 . 7 3 4 0 . 5 9 7 0 . 4 8 4 0 . 3 9 2 0 . 3 1 7 3 0 0 . 7 1 0 . 5 7 7 0 . 4 6 8 0 . 3 7 9 0 . 3 0 6 3 1 0 . 6 8 7 0 . 5 5 9 0 . 4 5 3 0 . 3 6 7 0 . 2 9 7 3 2 0 . 6 6 6 0 . 5 4 1 0 . 4 3 9 0 . 3 5 5 0 . 2 8 7 ex a m p l e ca l c ul a t i o n s go al : i m p l em en t a f i l t er wi th an in p u t s a m p le ra t e o f 100 mh z r e q u ir in g 100 db o f alias r e jec t io n f o r a 1.4 mh z p a s s band . so l u t i o n : f i r s t d e t e rm in e t h e p e r c e n ta g e o f th e sa m p le ra t e th a t is r e p r es en t e d b y t h e p a s s b a n d . 4 . 1 mhz 100 mhz 4 . 1 100 = = i n t h e ?100 db col u mn in t a b l e 13, f i n d t h e val u e g r ea t e r tha n o r e q ual t o t h e p a s s -b and p e r c e n t a ge o f t h e clo c k ra te . th en f i n d t h e co r r es p o n d in g ra t e de ci ma t i o n fac t o r ( m ci c ). f o r a n m ci c o f 6, th e f r eq uen c y tha t has ?100 db o f alias r e jec t io n is 1.48%, which is s l ig h t l y la rg er tha n t h e 1.4 % ca lc u l a t e d . ther efo r e , fo r this exa m ple , t h e maxim u m b o u n d o n c i c decima tio n r a t e is 6. a hig h er m ci c m e an s les s alias r e j e c t io n tha n t h e 100 db r e q u ir ed . fir half-band bl ock the o u t p u t o f t h e c i c f i l t er is p i p e li n e d in t o t h e fir h b (half- b a nd) bl o c k. e a ch chan nel has t w o s e ts of c a s c a d ing f i xe d - co ef f i cien t fir a n d f i xe d-c o ef f i cien t half- b an d f i l t ers. the half- b a nd f i l t ers de ci ma t e b y 2. e a ch o f t h es e f i l t ers ( f ir1, hb1, f i r2, hb2) a r e des c r i b e d i n t h e fol l o w in g s e c t i o n s . 3- t a p f i x e d- co efficient f ilte r ( f ir1) the 3-t a p fir f i l t er is us ef u l in cer t a i n f i l t er conf igura t io n s i n w h ich ext r a a l ia s p r o t e c t i o n is ne e d e d fo r t h e de cima t i n g hb1 f i l t er . i t is a sim p le s u m-o f - p r o d u c t s fir f i l t er wi t h t h r e e f i l t er t a ps and 2- b i t f i xe d co ef f i cien ts. n o t e t h a t t h is f i l t er do es n o t de cima t e . the c o ef f i cien ts o f t h is symm et r i c f i l t er a r e {1, 2, 1}. the n o r m alize d co ef f i cien ts us e d in t h e im ple m en t a t i o n a r e {0.25, 0.5, 0.25}. the us er can ei t h er us e o r b y p a s s t h is f i l t er . w r i t in g l o g i c 0 t o t h e fir1 enab le b i t in t h e fi r - hb co n t r o l r e g i s t er b y p a s s es t h i s f i xe d-co ef f i cien t f i l t er . the f i l t e r is us ef u l o n ly in cer t a i n f i lt er co nf igura t io n s a n d b y p a ssing i t fo r o t h e r a p plic a t io n s r e su lts in po w e r sa vi n g s . 04998-0-031 fraction of fir1 input sample rate 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 dbc 0 ? 16.67 ?8.33 ? 33.33 ? 25.00 ? 50.00 ? 41.67 ? 66.67 ? 58.33 ? 83.33 ? 75.00 ?100.00 ? 91.67 0.34 0.66 ?8 1 fir1 response f i gur e 3 1 . fir1 f i lt er re sp o n se to the input r a te o f the f i lt er
AD6636 rev. 0 | page 30 of 72 t h i s f i l t e r r u n s a t t h e s a m e s a m p l e r a t e a s t h e c i c f i l t e r o u t p u t ra t e and is gi v e n b y cic in fir m f f = 1 wher e: f in is t h e in p u t ra t e in t o t h e cha n n e l. m cic i s t h e d e cim a ti o n ra ti o in th e ci c f i l t e r s t a g e . the maxi m u m i n p u t and o u t p u t ra t e s fo r t h is f i l t er a r e 150 mh z. d e cimat e -b y-2 half-ba n d f ilter (hb 1 ) the n e xt s t a g e o f t h e fir - hb blo c k is a de c i ma t e -b y-2 half- b a nd f i l t er . th e 11-t a p , s y mm et r i cal, f i xe d-co ef f i cien t hb1 f i l t e r has lo w p o w e r co n s um p t io n d u e t o i t s p o l y p h as e im p l e m e n t a - ti o n . th e f i l t e r h a s 22 b i t s o f i n p u t a n d o u t p u t da ta wi th 10-b i t co ef f i cien ts. t a ble 14 lis t s t h e co ef f i cien ts o f t h e half-b an d f i lt er . the n o r m alize d co ef f i cien ts us e d in t h e im ple m en t a t i o n an d t h e 10- b i t de c i mal e q ui vale n t val u e o f t h e co e f f i cien ts a r e als o lis t e d . o t h e r co ef f i cien ts a r e ze r o s. table 14. fixe d coefficie n ts fo r hb1 filter coefficient number normalize d coefficient decimal coeffi cient (10-bit) c1, c11 0.013671875 7 c3, c9 ?0.103515625 ?53 c5, c7 0.58984375 302 c 6 1 5 1 2 simi l a r t o t h e f i r1 f i l t er , t h is f i l t er ca n b e us e d o r b y p a s s e d . w r i t in g l o g i c 0 t o th e hb1 enab le b i t in t h e fi r -hb con t r o l r e g i s t er b y p a s s e s t h is f i xe d-co ef f i cien t hb f i l t er . the f i l t er is us ef u l o n ly in c e r t a i n f i l t er co nf igura t io n s an d b y p a ssin g i t fo r o t h e r a p p l ica t io n s r e s u l t s in po w e r sa vin g s. f o r exa m p l e , i t is us ef u l in na r r o w -b and and w i deb a n d o u t p ut a p plic a t ion s in w h ich m o r e f i lter in g is r e q u ir e d as com p a r e d to v e r y wide b a ndwi d t h a p pl ica t ion s i n w h ich a hig h er o u t p u t ra t e mig h t p r ohi b i t t h e us e o f a de cima t i n g f i l t er . th e r e sp on s e o f t h e f i lt er is s h o w n in f i gur e 32. the i n p u t s a m p le ra t e o f t h is f i lt er is t h e s a me as t h e c i c f i l t er o u t p u t ra te an d is gi v e n b y cic in hb m f f = 1 wher e: f in is t h e in p u t ra t e in t o t h e cha n n e l. m cic i s t h e d e cim a ti o n ra ti o in th e ci c f i l t e r s t a g e . 04998-0-032 fraction of hb1 input sample rate 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 dbc 0 20 10 40 30 60 50 80 70 110 100 90 120 hb1 response 0.43 0.57 ?7 7 f i g u re 32. hb 1 f i l t e r r e s p ons e t o the input r a te o f the f i lt er the f i l t er has a maxim u m in p u t s a m p le r a t e o f 150 mh z and , w h e n f i l t er is n o t b y p a ss e d , t h e max i m u m ou t p ut r a te is 75 mh z. the f i l t er has a r i p p le o f 0.0012 db an d r e j e c t ion o f 77 db . f o r a n a l ias r e j e c t ion o f 77 db , t h e a l ias- p r o t e c t e d b a ndwid t h is 14 % o f t h e f i l t er i n pu t s a m p le r a t e . the b a ndwid t h o f t h e f i l t er fo r a r i p p le o f 0.00075 db is als o th e s a me as t h e al ias-p r o t ec t e d b a ndwi d t h, d u e t o t h e na t u r e o f half-b an d f i lt ers. th e 3 db ba ndwid t h o f this f i l t er is 44% o f th e f i l t er in p u t sa m p le ra t e . f o r exa m ple , if th e s a m p le ra t e i n t o t h e f i l t er is 50 mh z, t h en t h e al ias - p r o t e c te d b a ndwid t h of t h e hb1 f i l t er is 7 mh z. i f t h e ba n d w i d t h o f th e r e q u i r ed ca rri e r i s gr ea t e r th a n 7 m h z , th en hb1 mig h t n o t b e us ef u l . 04998-0-033 fraction of hb1 input sample rate 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 dbc 0 ?20 ?10 ?40 ?30 ?60 ?50 ?80 ?70 ?100 ?90 ?120 ?110 ?107 fir1 + hb1 response 0.43 0.57 f i g u re 33. co mpos i t e r e s p o n s e of fir 1 and hb 1 f ilt ers t o thei r input rat e
AD6636 rev. 0 | page 31 of 72 6- t a p f i x e d co efficient f ilte r ( f ir2) f o l l o w in g t h e f i rs t cas c ade o f t h e fir1 a n d hb1 f i l t ers is t h e s e con d cas c ade o f t h e fir2 an d hb2 f i l t ers. the 6-t a p , f i xe d- co ef f i cien t fir2 f i l t er is us ef u l in p r o v idi n g ext r a alias p r o t ecti o n f o r th e deci ma ti n g h b 2 f i l t e r i n cer t a i n f i l t e r co nf igura t io n s . i t is a sim p le su m-o f -p r o d u c t s fir f i l t er w i t h s i x f i l t er t a ps and 5 - b i t f i xe d co ef f i cien ts. n o t e t h a t t h is f i l t er do es n o t de cima t e . th e n o r m ali z e d c o ef f i cien ts us e d in t h e i m p l em en ta ti o n a n d t h e 5-b i t deci m a l eq ui v a len t v a l u e o f t h e co ef f i cien ts a r e lis t e d in t a b l e 1 5 . table 15. 6 - ta p fir1 filter c o efficients coefficient number normalie d coefficient decimal coeffi cient (5-bit) c0, c5 ?0.125 ?2 c1, c4 0.1875 3 c2, c3 0.9375 15 the us er can ei t h er us e o r b y p a s s t h is f i l t er . w r i t in g l o g i c 0 t o fir2 ena b le b i t in t h e fir - hb c o n t r o l r e g i s t er b y p a s s es t h is f i xe d-co ef f i cien t f i l t er . the f i l t e r is us ef u l o n ly in cer t a i n f i lt er co nf igura t io n s a n d b y p a ssing i t fo r o t h e r a p plic a t io n s r e su lts in p o w e r s a v i n g s. the f i l t er is es p e cial ly us ef u l in in cr e a si n g t h e s t o p -b and a t t e n u a t ion o f t h e h b 2 f i l t er t h a t fol l o w s. th er efo r e , i t is o p t i ma l t o us e b o t h fir2 and hb2 i n a conf igura t io n. t h is f i l t er r u n s a t a s a m p le r a t e gi v e n b y o n e o f th e f o l l o w in g eq ua ti o n s : f fi r2 = f hb1 , i f hb 1 i s by pa ss ed f fi r2 = 2 hb1 f , i f hb1 i s n o t b y pas sed wher e f hb1 is t h e in p u t r a t e o f t h e hb1 f i l t er . t h e m a xim u m in p u t and o u t p u t ra t e f o r this f i l t er is 75 mh z. t h e r e s p o n se o f th e fir2 f i l t er is s h o w n in f i gur e 34. 04998-0-034 fraction of fir2 input sample rate 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 dbc 0 ?8.33 ? 16.67 ? 25.00 ? 33.33 ? 41.67 ? 50.00 ? 58.33 ? 66.67 ? 75.00 ? 83.33 ? 91.67 ?100.00 ?30 0.39 fir2 response 0.61 f i gur e 3 4 . fir2 f i lt er re sp o n se to the input r a te o f the f i lt er d e cimat e -b y-2 half-ba n d f ilter (hb 2 ) the s e cond s t a g e o f t h e s e cond cas c ade o f t h e f i r -hb b l o c k is a decima t e -b y-2 half-ban d f i l t er . the 27-t a p , sy mm et r i c, f i xe d- co ef f i cien t hb2 f i l t er has lo w p o w e r co n s um p t i o n d u e t o i t s p o lyphas e i m pl em e n t a t i on. the f i l t er has 20 b i ts o f in p u t an d o u t p u t da t a wi t h 12- b i t c o ef f i cien ts. th e n o r m alize d co ef f i cie n ts us ed in t h e im p l em en t a tion an d th e 10-b i t dec i mal eq ui valen t val u e o f t h e co e f f i cien ts a r e lis t e d i n t a b l e 16. o t h e r co ef f i cien ts are z e ro s . table 16. hb2 filter fixed co efficients coefficient number normalie d coefficient decimal coeffi cient (12-bit) c1, c27 0.00097656 2 c3, c25 ?0.00537109 ?11 c5, c23 0.015 32 c7, c21 ?0.0380859 ?78 c9, c19 0.0825195 169 c11, c17 0.1821289 ?373 c13, c15 0.6259766 1282 c 1 4 1 2 0 4 8 simi l a r t o t h e h b 1 f i l t er , t h e us e r ca n e i t h er us e o r b y p a s s t h is f i l t er . w r i t in g l o g i c 0 t o t h e h b 1 ena b le b i t in t h e fir -hb co n t r o l r e g i s t er b y p a s s es t h is f i xe d-co ef f i cien t hb f i l t er . the f i l t er is us ef u l o n ly in cer t a i n f i lt er co nf igura t ion s an d b y p a ssi n g i t f o r o t h e r a p p l ica t io n s r e s u l t s in po w e r sa vin g s. f o r exa m p l e , t h e f i l t er is us ef u l in na r r o w -b and a p pli c a t io n s in w h ich m o r e f i l t er in g is r e q u i r e d , as co m p a r e d t o w i de -b and a p plic a t ion s , in which a hig h er o u t p u t ra te mig h t p r ohib i t t h e us e o f a de cima t - in g f i l t er . th e r e s p o n s e o f t h e h b 2 f i l t er is s h own in f i gur e 35. 04998-0-035 fraction of hb2 input sample rate 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 dbc 0.01 ? 19.99 ? 29.99 ?9.99 ? 39.99 ? 49.99 ? 60.00 ? 70.00 ? 80.00 ? 90.00 ?100.00 ?110.00 ?120.00 ?6 5 0.66 0.34 hb2 response f i g u re 35. hb 2 f i l t e r r e s p ons e t o the input r a te o f the f i lt er
AD6636 rev. 0 | page 32 of 72 the f i l t er i n p u t s a m p le ra t e is t h e s a me as t h e fir2 f i l t er o u t p u t r a te a n d i s g i ve n by one of t h e f o l l ow i n g e q u a t i ons : f hb2 = f fi r2 = f hb1 , i f h b 1 i s by pa ss ed f hb2 = f fi r2 = 2 hb1 f , i f hb 1 i s no t by p a ss ed wher e: f fi r1 is t h e in p u t ra t e o f t h e fir1 f i l t er . f hb1 is t h e i n p u t ra t e o f t h e hb1 f i l t er . the i n p u t t o t h e f i l t er has a max i m u m o f 75 mh z. the maxim u m o u t p u t ra t e w h en n o t b y p a s s e d is 37. 5 mh z. the f i l t er has a r i p p le o f 0.00075 db an d r e j e c t io n o f 81 db . f o r a n a l ias r e j e c t ion o f 81 db , t h e a l ias- p r o t e c t e d b a ndwid t h is 33 % o f t h e f i l t er i n pu t s a m p le r a t e . the b a ndwid t h o f t h e f i l t er fo r a r i p p le o f 0.00075 db is the s a m e as alias-p r o t ec ted bandwid t h, d u e t o t h e na t u re o f half-b an d f i l t ers. the 3 db b a ndwid t h o f t h is f i l t er is 47% o f t h e f i l t er i n pu t s a m p le r a t e . f o r exa m ple , if t h e s a m p le ra t e in t o t h e f i l t er is 25 mh z, t h en t h e al ias - p r o t ec t e d ban d wid t h o f t h e hb 2 f i l t er is 8.25 mh z (33 % o f 25 mh z). i f t h e b a ndwi d t h o f t h e r e q u ir e d ca r r i er is g r e a t e r tha n 8.25 m h z, th en hb2 mig h t n o t b e us ef u l . 04998-0-036 fraction of hb2 input sample rate 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 dbc 0.01 ? 19.99 ? 29.99 ?9.99 ? 39.99 ? 49.99 ? 60.00 ? 70.00 ? 80.00 ? 90.00 ?100.00 ?110.00 ?120.00 ?90 0.66 0.34 fir2 + hb2 response f i gur e 3 6 . c o m p o s it e resp onse o f fir1 a n d h b 1 fil t ers to their input ra tes intermed i a te d a t a router f o l l o w in g t h e f i r -hb cas c ade f i l t ers is t h e in t e r m e d i a te da t a r o u t e r . t h i s da t a r o u t e r co n s i s ts o f m u x e s th a t allo w th e i a n d q da t a f r o m an y cha n n e l f r o n t e n d (in p u t p o r t + n c o + cic + fir - h b ) t o be p r oce s sed b y a n y c h a n n e l ba ck en d (mr c f + d r cf + cr cf) . th e ch o i c e o f cha n n e l f r o n t e n d is made b y p r ogra m m i n g a 3-b i t mr cf da t a se lec t w o r d in th e mrcf co n t r o l r e g i s t er . the vali d val u es fo r t h is w o r d a n d t h e i r co r r es p o n d in g s e t t i n gs a r e lis t e d in t a b l e 17. table 17. data router select s e ttings mrcf data select [2:0] data source 0 0 0 c h a n n e l 0 0 0 1 c h a n n e l 1 0 1 0 c h a n n e l 2 0 1 1 c h a n n e l 3 1 x 0 c h a n n e l 4 1 x 1 c h a n n e l 5 a l lo win g dif f er en t chann e l b a ck e n ds t o s e le c t dif f er en t cha n ne l f r o n t en ds is us ef u l in t h e p o ly phas e i m ple m e n t a t i o n o f f i l t ers . w h en m u l t i p le AD6636 c h a n nels a r e us ed t o p r o c es s a sin g l e ca r r i er , a sin g le-cha nn e l f r o n t e n d fe e d s m o r e t h a n on e chann e l b a ck e n d. af ter p r o c ess i ng t h rou g h t h e chan nel b a ck e n ds ( r c f f i l t ers), t h e da t a is in t e rle a v e d b a ck f r o m al l t h e p o lyphas e d chan nel s . mono -r a t e r a m c o efficient fil t e r (mrcf) the mr cf is a p r og ra mma b l e s u m-o f - p r o d u c t s fir f i l t er . this f i l t er b l o c k comes a f t e r t h e f i rst da t a r o u t er a n d b e fo r e t h e d r cf a n d crcf p r ogra m m a b l e f i l t er s. i t co n s is ts o f a maxim u m o f ei g h t t a ps wi t h 6 - b i t p r og ra mma b l e co ef f i cien ts. n o te t h a t t h is b l o c k do es n o t de cima te an d is us e d as a h e lp er f i l t er fo r t h e d r cf a n d crcf f i l t ers t h a t fol l o w in t h e sig n al chain. the n u m b er o f f i l t er t a ps t h a t ar e t o b e c a lc u l a t e d is p r og ra m- ma b l e usin g t h e 3-b i t n u m b er -of-t a ps w o r d in t h e mrcf co n t r o l r e g i s t er o f t h e cha n ne l u n der con s idera t io n. th e 3- b i t w o r d p r og ra mm e d is on e les s t h a n t h e n u m b e r o f f i l t er t a ps. the co ef f i cien ts t h ems e lv es a r e p r og ra mm e d in eig h t mrcf co ef f i cien t m e m o r y r e g i s t ers fo r in di v i d u al cha nne ls. th e i n pu t an d output d a t a to t h e bl o c k are b o t h 2 0 - b i t . s y mmet r y th o u g h t h e mrcf f i l t er do es no t r e q u ir e symm et r i cal f i lt ers, if t h e f i l t er is symm et r i cal, t h e n t h e s y mm et r y b i t in t h e mrcf co n t r o l r e g i s t er s h o u ld b e s e t. w h en t h is b i t is s e t, o n ly half o f t h e i m p u ls e r e sp o n s e n e e d s t o b e p r og ra mm e d in t o t h e mr cf co ef f i cien t m e m o r y r e g i s t ers. f o r exa m ple , if th e n u m b er o f f i l t er t a ps is e q u a l t o f i v e o r six a n d t h e f i l t er is symm et r i cal, t h e n on ly t h re e c o e f f i c i e n t s ne e d to b e wr i tte n i n to t h e c o e f f i c i e n t me mor y . f o r b o t h s y m m e t r i c a l a n d a s y m me t r i c a l f i l t ers, t h e n u m b er o f f i l t er t a ps is limi te d t o e i g h t. clock r a t e t h e mr cf f i l t er r u n s o n a n in ter n al high s p ee d p ll c l o c k. t h is c l o c k ra t e can b e as hig h as 200 mh z. i f t h e half c l o c k ra t e b i t in th e mrcf co n t r o l r e gis t er is set, th en o n l y half th e pll c l o c k ra t e is us e d (maxim um o f 100 mh z). this r e su l t s in p o w e r s a vin g s, b u t can o n l y be us e d if cer t a i n con d i t ion s a r e m e t.
AD6636 rev. 0 | page 33 of 72 b e ca us e t h is f i l t er is n o n d e c i m a t in g, t h e i n p u t and o u t p u t ra t e s a r e b o t h s a m e and e q u a l t o on e o f t h e fol l o w in g : f mr c f = f hb2 , if h b 2 i s by p a ss e d f mr c f = 2 hb2 f , i f h b 2 i s no t by pa ss ed if f pl lc l k is t h e pll clo c k and if 2 pllclk taps mrcf f n f th en half o f th e p ll c l o c k ca n b e used f o r p r o c es sin g (p o w er sa vi n g s ) . oth e r w i s e , t h e p l l c l oc k s h o u l d be used . bypass t h e mr cf f i l t er ca n be use d in n o r m al o p er a t io n o r b y p a s s e d usin g t h e mrc f b y p a s s b i t in t h e mrcf co n t rol r e g i s t er . w h e n t h e f i l t er is b y p a s s e d , t h e o u t p u t o f t h e f i l t er is t h e s a m e as t h e in p u t o f t h e f i l t e r . b y p a s s in g t h e mr cf f i l t er w h en n o t r e q u ir e d r e s u l t s in p o w e r s a vin g s. s c aling the o u t p u t o f t h e mrcf f i l t er ca n b e s c ale d b y usin g t h e 2- b i t m r c f s c a l i n g word i n t h e m r c f c o n t ro l re g i s t e r . t a bl e 1 8 s h o w s t h e vali d val u es fo r t h e 2- b i t w o r d and t h eir co r r es p o n d - in g s e t t in gs. table 18. mrc f scaling factor settings mrcf scale wo rd [1:0] scaling factor 00 18.06 db attenuation 01 12.04 db attenuation 10 6.02 db attenua t ion 11 no scaling, 0 db decima t i n g r a m c o efficie n t fil t er (drcf ) f o l l o w in g t h e mr cf is t h e p r og ra mma b l e d r cf fir f i l t er . this f i l t er c a n c a lc u l a t e u p t o 64 asymm e t r ical f i l t er t a ps o r u p t o 128 symm etr i cal f i l t er t a ps. th e f i l t er is als o ca p a b l e o f a p r og ra mma b l e decima tio n r a t e o f f r o m 1 t o 16. a f l exi b le co ef f i cien t o f fs et fe a t ur e al lo ws lo adin g m u l t i p l e f i l t ers in t o t h e co ef f i cien t r a m a n d cha n g i ng t h e f i l t ers o n t h e f l y . th e de cima t i o n phas e fe a t ur e al lo ws a p o lyphas e i m ple m en t a t i on, wher e m u l t i p le AD6636 c h a n nels a r e us ed f o r p r o c es sin g a s i n g l e c a rri e r . the d r cf f i l t er has 20-b i t in p u t an d o u t p u t da ta an d 14-b i t co ef f i cien t da t a . the n u m b er o f f i l t er t a ps t o cal c u l a t e is p r og ra mma b l e a n d is s e t in t h e d r cf t a ps r e g i s t er . the val u e o f t h e n u m b er of t a ps mi n us o n e is wr i t t e n t o t h is r e g i s t er . f o r exa m ple , a val u e o f 19 in t h e r e g i s t er co r r es p o n d s t o 20 f i l t er ta ps. t h e decim a tio n ra t e is p r ogra mm a b le usin g t h e 4-b i t d r cf d e c i m a t i on r a te word i n t h e dr c f c o n t ro l re g i s t e r . ag ai n , t h e val u e wr i t t e n is t h e de cima t i o n ra t e min us on e . bypass t h e d r cf f i l t er ca n be use d in n o r m al o p er a t io n o r b y p a s s e d usin g t h e d r cf b y p a s s b i t i n t h e d r cf co n t r o l r e g i s t er . w h e n t h e d r cf f i l t er is b y p a ss e d , n o s c a l in g is a p plie d an d t h e ou t p ut o f t h e f i l t er is t h e s a m e as t h e i n p u t t o t h e d r c f f i l t er . s c aling the o u t p u t o f t h e d r cf f i l t er ca n b e s c ale d usin g t h e 2- b i t d r cf s c aling wo r d in t h e d r cf co n t r o l r e g i s t er . t a b l e 19 lis t s t h e vali d val u es fo r t h e 2-b i t w o r d a n d t h eir co r r es p o ndin g se t t in g s . table 19. drc f scaling factor settings drcf scale word [1:0] scaling factor 00 18.06 db attenuation 01 12.04 db attenuation 10 6.02 db attenua t ion 11 no scaling, 0 db s y mmet r y the d r cf f i l t e r do es n o t r e q u i r e symm et r i cal f i l t ers. h o w e v e r , if t h e f i l t er is sy mmet r ical, t h e n t h e sy mm et r y b i t in t h e d r cf co n t r o l r e g i s t er s h o u ld b e s e t. w h en t h is b i t is s e t, o n ly half o f t h e i m p u ls e r e sp o n s e n e e d s t o b e p r og ra mm e d in t o t h e d r cf co ef f i cien t m e m o r y r e g i s t ers. f o r exa m ple , if th e n u m b er o f f i l t er ta ps is eq u a l t o 15 o r 16 a n d the f i l t er is sy mmetr ical , th en o n ly eig h t co ef f i cien ts n e e d t o b e wr i t t e n i n t o t h e co ef f i cien t me mor y . b e c a u s e a tot a l of 6 4 t a p s c a n b e w r itt e n i n to t h e me mor y re g i ste r s , t h e drc f c a n p e r f or m 6 4 a s y m me t r i c a l f i lte r ta ps o r 128 symm etr i cal f i l t er ta ps. c o efficient o f f s et m o r e t h a n on e s e t o f f i l t er co ef f i cien ts c a n b e l o ade d i n t o co ef f i cien t r a m a t an y g i v e n t i me (g i v en s u f f icien t r a m s p ace). th e co ef f i cien t o f fs et can b e used in th is cas e t o acces s t h e tw o o r m o r e dif f er en t f i l t ers. b y cha n g i n g t h e co ef f i cien t o f fs et, t h e f i l t er co ef f i cien ts b e i n g acces s e d ca n b e chan g e d o n t h e f l y . this de c i mal o f fs et val u e is p r og ra mm e d in t h e dr cf co ef f i cien t o f fs et r e g i s t er . w h en t h is val u e is cha n g e d d u r i n g t h e c a l c ul a t i o n o f a pa r t i c ul a r o u t p u t da t a sa m p l e , th e sa m p l e calc u l a t ion is com p let e d usin g t h e old c o ef f i cien ts, an d t h e ne w co ef f i cien t o f fs et f r o m t h e n e xt da t a s a m p le calc u l a t ion is us e d . dec i m a t i o n pha s e w h en m o r e than on e c h a n ne l of AD6636 is us e d t o p r o c es s on e ca r r i er , p o lypha s e im ple m e n t a t i o n o f co r r es p o ndin g chann e ls d r cf o r cr cf is p o ssi b le using t h e de cima t i on phas e fe a t ur e . this fe a t ur e can be us e d o n l y un der cer t a i n con d i t io ns. th e d e cima tio n p h ase is p r ogra m m e d usin g t h e 4-b i t d r cf d e c i m a t i on ph a s e word of t h e drc f c o n t ro l re g i ste r .
AD6636 rev. 0 | page 34 of 72 maxim u m nu mb e r of t a ps c a lculate d the o u t p u t r a t e o f t h e d r cf f i l t er is g i v e n b y drcf mrcf drcf m f f = wher e: f mr c f i s t h e d a t a r a t e o u t o f t h e m r c f f i l t e r a n d i n t o t h e d r c f fi l t e r . m drc f is t h e dec i m a tio n ra t e in t h e d r cf f i l t er . t h e d r cf f i l t er co n s is ts o f two m u l t i p lier s (o n e each f o r th e i a n d q p a t h s ) . e a c h m u l t i p l i e r , w o r k i n g a t t h e h i g h s p e e d c l o c k ra t e (p ll c l o c k ) , ca n d o o n e m u l t i p l y (o r o n e t a p) per h i gh s p e e d clo c k c y cle . ther efo r e , t h e maxim u m n u m b er o f f i l t er ta ps th a t ca n be calcula t ed (s ymm e tri c al o r as ym m e tri c al f i l t e r ) is g i v e n b y 1 ? ? ? ? ? ? ? ? ? = drcf pllclk f f ceil taps of number maximum wher e: f pl lc lk is th e hig h s p e e d in ter n al p r o c es sin g c l o c k g e n e ra ted b y t h e pll clo c k m u l t i p lier . f drc f is th e o u t p u t ra t e o f t h e dr cf f i l t er calc ula t ed abo v e . pro g r a mming drcf r e gist ers for a n asymmet r ic al f ilt er t o p r og ra m t h e d r cf r e g i s t ers fo r a n asymm e t r ical f i l t er : 1. wr i t e nt aps C 1 in t h e d r cf t a ps r e g i s t er , w h er e nt ap s is t h e n u m b er o f f i l t er t a ps. th e a b s o l u t e maxi m u m va l u e fo r nt ap s is 64 in as ymm e t r ica l f i l t er m o de . 2. w r i t e 0 fo r t h e d r cf co ef f i cien t o f fs et r e g i s t er . 3. w r i t e 0 fo r t h e s y mm et r i cal f i l t e r b i t i n t h e d r c f co n t r o l re g i ste r . 4. w r i t e t h e s t a r t addr es s fo r t h e c o ef f i cien t r a m, typ i cal l y e q ual t o t h e co e f f i cien t o f fs et r e g i s t er in t h e d r cf s t a r t addr es s r e g i st er . 5. i n t h e d r cf sto p addr es s r e g i st er , wr i t e t h e st op addr es s fo r t h e co ef f i cien t r a m, typ i cal l y e q ual t o t h e fol l o w in g: coeff i ci en t o f fse t + nt ap s ? 1 6. w r i t e al l co ef f i cien ts i n r e vers e o r der (s t a r t wi t h las t co ef f i cien t) t o t h e d r cf co ef f i cien t m e m o r y r e g i s t er . i f in 8 - bit m i c r op or t mo d e or s e r i a l p o r t mo d e , w r it e t h e l o we r b y t e o f t h e m e m o r y r e g i s t er f i rs t a n d t h en t h e hig h er b y t e . 7. af t e r eac h wr i t e acces s t o t h e dr cf co ef f i cien t m e m o r y r e g i s t er , t h e i n t e r n al r a m addres s is i n cr em e n te d s t a r t i n g wi t h t h e st a r t addr ess and e n di n g w i t h t h e sto p addr ess. n o t e t h a t e a ch wr i t e o r r e ad ac ces s i n cr emen ts t h e i n t e r n al r a m addr es s. th er efo r e , al l co e f f i cien ts sh o u ld b e r e ad f i rs t b e f o r e r e a d i n g t h e m b a c k . a l s o , f o r d e b u g g i n g p u r p o s e s , e a c h r a m addr ess c a n b e wr i tten i n divid u a l ly b y ma k i n g t h e st a r t addr es s and s t op addr es s e s t h e s a me . th er efo r e , t o p r og ra m o n e r a m lo c a t i o n , t h e us er wr i t es t h e addr es s o f t h e r a m lo c a t i on t o b o t h t h e s t a r t a n d s t o p addr e s s r e g i s t ers, an d t h e n wr i t es t h e c o e f f i c i e n t me mor y re g i ste r . pro g r a m m ing drcf r e gist e r s for a s y mm et ric f ilt er t o p r og ra m t h e d r cf r e g i s t ers fo r a symm et r i c a l f i l t er : 1. wr i t e nt aps C 1 in t h e d r cf t a ps r e g i s t er , w h er e nt ap s is t h e n u m b er o f f i l t er t a ps. th e a b s o l u t e maxi m u m va l u e fo r nt ap s is 128 in sy mm etr i c f i l t er m o de . 2. wr i t e ce i l (64 C nt ap s /2) fo r t h e d r cf co ef f i cien t o f fs et r e g i s t er , wher e t h e ce i l f u n c t i on t a k e s t h e clos est in teg e r gr ea t e r th a n o r eq u a l t o t h e a r gu m e n t . 3. w r i t e 1 fo r t h e s y mm et r i cal f i l t e r b i t i n t h e d r c f co n t r o l re g i ste r . 4. w r i t e t h e s t a r t addr es s fo r t h e c o ef f i cien t r a m, typ i cal l y e q ual t o co ef f i cien t o f fs et r e g i s t er , in t h e d r cf s t a r t addr es s r e g i st er . 5. w r i t e t h e s t o p addr es s fo r t h e c o ef f i cien t r a m, typ i cal l y eq u a l t o ceil( nt aps /2) C 1, in t h e d r cf s t o p addr es s re g i ste r . 6. w r i t e al l co ef f i cien ts t o t h e d r cf co ef f i cien t m e m o r y r e g i s t er , s t a r t i n g wi t h t h e mi ddl e o f t h e f i l t er and w o rking t o wa r d s t h e e n d o f t h e f i l t er . w h e n co ef f i cien t s a r e nu m b e r e d 0 t o nt ap s C 1, t h e middle co ef f i cien t is g i v e n b y th e co ef f i cien t n u m b er ceil( nt ap s /2). i f i n 8-b i t m i c r op or t mo d e or s e r i a l p o r t mo d e , w r ite t h e l o we r by te o f t h e m e m o r y r e g i s t er f i rs t and t h e n t h e hig h er b y t e . af t e r e a ch wr i t e ac cess t o t h e d r cf co ef f i cien t m e mo r y r e g i s t er , t h e i n t e r n al r a m addr es s is i n c r em e n t e d s t a r t i n g wi t h t h e st a r t addr ess and e n di n g wi t h sto p addr ess. n o t e t h a t e a ch wr i t e o r r e ad ac ces s i n cr emen ts t h e i n t e r n al r a m addr es s. th er efo r e , al l co e f f i cien ts sh o u ld b e r e ad f i rs t b e f o r e r e a d i n g t h e m b a c k . a l s o , f o r d e b u g g i n g p u r p o s e s , e a c h r a m addr ess c a n b e wr i tten i n divid u a l ly b y ma k i n g t h e st a r t a n d s t o p addr ess e s t h e s a m e . th er efo r e , t o p r og ra m o n e r a m lo ca t i on, t h e us er wr i t es t h e addr es s o f t h e r a m lo ca t i on t o b o t h t h e s t a r t and s t o p addr es s r e g i s t ers, a n d t h en wr i t es t h e c o e f f i c i e n t me mor y re g i ste r .
AD6636 rev. 0 | page 35 of 72 channel r a m c o efficient fil t er ( c rcf) f o l l o w in g t h e dr cf is t h e p r og ra mma b l e de ci ma t i n g cr cf fir f i l t er . th e only dif f er en ce b e tw e e n t h e d r cf a n d crcf f i l t ers is t h e co e f f i cien t b i t wi d t h. th e d r cf has 14-b i t co ef f i cien ts, whi l e t h e d r cf has 20-b i t co ef f i ci en ts. this f i l t er c a n c a lc u l a t e u p t o 64 asymm e t r ical f i l t er t a ps o r u p t o 128 symm etr i cal f i l t er t a ps. th e f i l t er is ca p a b l e o f a p r og ra mma b l e decima tio n r a t e f r o m 1 t o 16. th e f l exi b le co ef f i cien t o f fs et fe a t ur e al lo ws lo adin g m u l t i p l e f i l t ers in t o t h e co ef f i cien t r a m a n d cha n g i ng t h e f i l t ers o n t h e f l y . th e d e ci ma ti o n p h ase f e a t ur e allo ws f o r a po l y p h a s e i m p l em en t a - tio n in which m u l t i p le AD6636 c h a n n e ls a r e us ed t o p r o c es s a s i n g l e c a rri e r . the cr cf f i l t er has 20-b i t i n p u t a n d o u t p ut da t a an d 14 -b i t co ef f i cien t da t a . the n u m b er o f f i l t er t a ps t o cal c u l a t e is p r og ra mma b l e a n d is s e t in t h e cr cf t a ps r e g i st er . th e val u e o f t h e n u m b er o f t a ps mi n us o n e i s wr i t t e n t o t h is r e g i s t er . f o r exa m ple , a val u e o f 19 in t h e r e g i s t er co r r es p o nds t o 20 f i l t er ta ps. th e decima tio n ra t e is p r ogra m m a b l e usin g th e 4-b i t cr cf de cima t i o n ra te w o r d i n t h e c r cf co n t rol r e g i st er . a g ain, t h e va l u e wr i tte n is t h e d e cima t i o n r a te min us on e. bypass the cr cf f i l t er ca n b e us e d i n n o r m al o p er a t i o n o r b y p a s s e d usin g t h e c r cf b y p a ss b i t i n t h e cr cf co n t r o l r e g i st er . w h e n t h e c r cf f i l t er is b y p a ss e d , n o s c a l in g is a p plie d an d t h e ou t p ut o f t h e f i l t er is t h e s a m e as t h e i n p u t t o t h e cr c f f i l t er . s c aling the o u t p u t o f t h e c r cf f i l t er c a n b e s c ale d usi n g t h e 2 - b i t c r c f s c a l i n g w o rd i n t h e c r c f c o n t ro l re g i st e r . t a bl e 2 0 s h o w s t h e vali d val u es fo r t h e 2- b i t w o r d and t h e co r r es p o n d ing se t t in g s . | co e f f | is t h e s u m o f al l co ef f i cien ts (i n n o r m alize d fo r m ) us e d t o calc u l a t e t h e fir f i l t er . table 20. c r c f scaling factor settings crcf scale word [1:0] scaling factor 00 18.06 db attenuation 01 12.04 db attenuation 10 6.02 db attenua t ion 11 no scaling, 0 db s y mmet r y the cr cf f i l t er do es n o t r e q u ire symm et r i cal f i l t ers. h o w e v e r , if t h e f i l t er is sy mmet r ical, t h e n t h e sy mm et r y b i t in t h e cr cf co n t r o l r e g i s t er s h o u ld b e s e t. w h en t h is b i t is s e t, o n ly half t h e i m p u lse r e s p o n se n eed s t o be p r ogra m m ed i n t o th e c r c f co ef f i cien t m e m o r y r e g i s t ers. f o r exa m ple , if th e n u m b er o f f i l t er ta ps is eq u a l t o 15 o r 16 a n d the f i l t er is sy mmetr ic, th en o n ly eig h t co ef f i cien ts n e e d t o b e wr i t t e n i n t o t h e co ef f i cien t me mor y . b e c a u s e a tot a l of 6 4 t a p s c a n b e w r itt e n i n to t h e me mor y re g i ste r s , t h e c r c f c a n p e r f or m 6 4 a s y m me t r i c a l f i lte r ta ps o r 128 symm etr i cal f i l t er ta ps. c o efficient o f f s et m o r e t h a n on e s e t o f f i l t er co ef f i cien ts c a n b e l o ade d i n t o t h e co ef f i cien t r a m a t an y t i m e ( g i v en s u f f icien t r a m s p ace). th e co ef f i cien t o f fs et can b e us ed in this cas e t o acces s th e tw o o r m o r e dif f er en t f i l t ers. b y cha n g i n g t h e co ef f i cien t o f fs et, t h e f i l t er co ef f i cien ts bein g access ed ca n be c h a n g e d o n the f l y . this de cimal o f fs et v a l u e is p r og ra mm e d i n t h e crcf co ef f i cien t o f fs et r e g i s t er . w h en t h is v a l u e is cha n g e d d u r i n g t h e calc u l a - t i on of a p a r t i c u l ar output d a t a s a m p l e , t h e s a m p l e c a l c u l a t i o n i s co m p let e d using t h e old co ef f i cien ts and t h e ne w co ef f i cien t of f s e t i s brou g h t i n to e f f e c t f r om t h e ne x t d a t a s a m p l e calc u l a t ion. dec i m a t i o n pha s e w h en m o r e than on e c h a n ne l of th e AD6636 is us ed t o p r o c es s o n e ca r r i er , p o lyphas e i m ple m e n t a t i o n o f t h e c o r r es p o n d i n g cha n n e ls d r cf o r cr cf is p o ssi b le usin g t h e de cima t i o n p h as e fe a t ur e . this fe a t ur e ca n be us e d o n l y under cer t a i n co ndi t ion s . th e de cima t i o n phas e is p r og ra mme d usin g t h e 4-b i t crcf de c i ma t i on phas e w o r d o f t h e c r cf co n t r o l re g i ste r . maxim u m nu mb e r of t a ps c a lculate d the o u t p u t r a t e o f t h e cr cf f i l t er is g i v e n b y crcf drcf crcf m f f = wher e: f drc f is t h e da t a ra t e o u t o f t h e d r cf f i l t er a n d in t o t h e crcf fi l t e r . m cr c f is the dec i m a tio n ra t e in t h e cr cf f i l t er . the cr cf f i l t er co n s is ts o f tw o m u l t i p liers (on e e a ch fo r t h e i a n d q p a t h s ) . e a c h m u l t i p l i e r , w o r k i n g a t t h e h i g h s p e e d c l o c k ra t e (p ll c l o c k ) , ca n m u l t i p l y ( o r ta p o n ce). th er ef o r e , th e max i m u m n u m b er o f f i l t er t a ps t h a t c a n b e ca lc u l a t e d ( s y m me t r i c a l or a s y m me t r i c a l f i lte r ) i s g i ve n by 1 ? ? ? ? ? ? ? ? ? = wher e: f pl lc lk is t h e hig h s p e e d i n ter n al p r o c es sin g clo c k g e n e ra te d b y t h e pll clo c k m u l t i p lier . f cr cf is t h e o u t p u t ra t e o f t h e cr cf f i l t er as cal c ula t e d pre v i o u s l y .
AD6636 rev. 0 | page 36 of 72 programming crcf registers for an asymmetrical filter to program the crcf registers for an asymmetrical filter: 1. wr ite ntaps C 1 in the crcf taps register, where ntaps is the number of filter taps. the absolute maximum value for ntaps is 64 in asymmetrical filter mode. 2. write 0 for the crcf coefficient offset register. 3. write 0 for the symmetrical filter bit in the crcf control register. 4. in the crcf start address register, write the start address for the coefficient ram, typically equal to the coefficient offset register. 5. in the crcf stop address register, write the stop address for the coefficient ram, typically equal to the following: coefficient offset + ntaps C 1 6. write all coefficients in reverse order (start with last coefficient) to the crcf coefficient memory register. in 8-bit microport mode or serial port mode, write the lower byte of the memory register first and then the higher byte. in 16-bit microport mode, write the lower 16-bits of the crcf memory register first and then the high four bits. after each write access to the crcf coefficient memory register, the internal ram address is incremented starting with the start address and ending with the stop address. note that each write or read access increments the internal ram address. therefore, all coefficients should be read first before reading them back. also, for debugging purposes, each ram address can be written individually by making the start and stop addresses the same. therefore, to program one ram location, the user writes the address of the ram location to both the start and stop address registers, and then writes the coefficient memory register. programming crcf registers for a symmetrical filter to program the crcf registers for a symmetrical filter: 1. wr ite ntaps C 1 in the crcf taps register, where ntaps is the number of filter taps. the absolute maximum value for ntaps is 128 in symmetrical filter mode. 2. wr ite ceil (64 C ntaps /2) for the crcf coefficient offset register, where the ceil function takes the closest integer greater than or equal to the argument. 3. write 1 for the symmetrical filter bit in the crcf control register. 4. in the crcf start address register, write the start address for the coefficient ram, typically equal to the coefficient offset register. 5. in the crcf stop address register, write the stop address for the coefficient ram, typically equal to ceil ( ntaps /2) C 1. 6. write all coefficients to the crcf coefficient memory register, starting with middle of the filter and working towards the end of the filter. when coefficients are numbered 0 to ntaps C 1, the middle coefficient is given by the coefficient number ceil ( ntaps /2). in 8-bit microport mode or serial port mode, write the lower byte of the memory register first and then the higher byte. in 16-bit microport mode, write the lower 16-bits of the crcf memory register first and then the high four bits. after each write access to the crcf coefficient memory register, the internal ram address is incremented starting with the start address and ending with the stop address. note that each write or read access increments the internal ram address. therefore, all coefficients should be read first before reading them back. also, for debugging purposes, each ram address can be written individually by making the start and stop addresses the same. therefore, to program one ram location, the user writes the address of the ram location to both the start and stop address registers, and then writes the coefficient memory register. interpolating half-band filter the AD6636 has interpolating half-band fir filters that immediately follow the crcf programmable fir filters and precede the second data router. each interpolating half-band filter takes 22-bit i and 22-bit q data from the preceding crcf and outputs rounded 22-bit i and 22-bit q data to the second data router. a 10-tap fixed-coefficient filter is implemented in this stage. the maximum input rate into this block is 17 mhz. conse- quently, the maximum output is constrained to 34 mhz. the normalized coefficients used in the implementation and the 10-bit decimal equivalent value of the coefficients are listed in table 21. other coefficients are 0. table 21. interpolating hb filter fixed coefficients coefficient number normalized coefficient decimal coefficient (10-bit) c1, c11 0.02734375 14 c3, c9 ?0.12890625 ?66 c5, c7 0.603515625 309 c6 1 512 the half-band filters interpolate the incoming data by 2. for a channel running at 2 the chip rate, the half-band can be used to output channel data at 4 the chip rate. the interpolation operation creates an image of the baseband signal, which is filtered out by the half-band filter.
AD6636 rev. 0 | page 37 of 72 the ima g e r e j e c t io n o f t h is f i l t e r is a b o u t 55 db , b u t is st i l l s u f f i cien t, b e c a us e t h e ima g e is f r o m t h e desir e d sig n al, n o t an in t e r f er in g sig n a l . n o t e t h a t t h e in t e r p ol a t ing h a lf-b an d f i lt er ca n be ena b le d b y wr i t in g a l o g i c 1 t o b i t 9 o f th e mrcf c o n t ro l re g i ste r s . t h e f r e q u e nc y re sp ons e of t h e i n te r p o l a t i n g h a l f - b a n d f i r i s s h o w n in f i gur e 37 wi t h r e s p ec t t o th e c h i p ra te . t h e in p u t ra t e t o this f i l t er is 2 th e c h i p ra te , a n d t h e o u t p u t ra t e is 4 t h e chi p r a te. 04998-0-037 frequency as fraction of input rate 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 dbc 0 ?20 ?40 ?60 ?80 ?100 ?5 3 0.75 1.25 interpolating halfb and filter response f i gure 37. inte rpo l ating ha lf-ba n d f r equenc y r e s p ons e outpu t d a t a router the o u t p u t da t a r o u t er cir c ui t pr e c e d es t h e six a g cs o f t h e f i nal output bl o c k a n d i m me d i ately f o l l ow s t h e i n te r p o l a t i n g h a l f - b a nd f i l t ers. this b l o c k co n s ists o f tw o s u b b l o c ks. th e f i rst subb l o c k is r e sp o n si b l e fo r com b inin g (i n t erle a v in g) da t a f r o m m o r e t h an on e cha n n e l i n to a s i n g le st r e am o f d a t a . the s e cond subb lo ck c a n p e r f o r m tw o sp e c ia l f u n c t i o n s, e i t h er co m p lex f i l t er co m p let i o n o r b i phas e f i l t er ing. the com b i n e d da ta is p a s s e d o n t o the a g cs. inte rleaving d a ta i n s o m e cas e s, f i l t er in g usin g a s i n g le cha n ne l is in suf f icien t . f o r s u ch s e t u ps, i t is adva n t a g e o us t o co m b i n e t h e f i l t er in g re s o u r c e s of more t h an o n e ch a n n e l. m u l t i p le c h a n ne ls ca n be set u p t o w o r k o n t h e ad c in p u t p o r t da t a wi t h t h e s a m e n c o an d f i lt er s e t u ps. the de cima t i o n phas e val u es i n o n e o f t h e r c f f i l t ers a r e s e t s u ch t h a t t h e cha n n e l f i l t ers a r e exac t l y o u t o f phas e wi t h e a ch o t h e r . i n t h e da t a r o u t er , t h es e m u l t i p le cha n n e ls a r e i n terle a v e d (com b i n e d) t o f o r m a sin g le s t r e a m o f da t a . b e ca us e eac h individ u al c h a n nel i s d e c i m a te d more t h an it wou l d b e i f a s i ng l e c h an nel we re f i l t er in g, a l a rg er n u m b er o f f i l t er t a ps can b e c a lc u l a t e d . f o r exa m p l e , tw o c h a nne ls need t o w o r k t o g e ther t o p r o d uce a f i l t er a t an o u t p u t ra t e o f 10 mh z w h en t h e in p u t ra te is 100 mh z. e a c h c h a n n e l is decima t e d b y a fac t o r o f 20 (t o t al de cim a t i o n ) to achie v e t h e desi r e d o u tp u t r a te o f 5 mh z e a ch. this com p a r es to a decima tion o f 10, if a sin g le c h a n n e l w e r e fi l t e r i n g . the s a m e c o ef f i cien ts a r e p r og ra mm e d in b o t h cha n n e ls r c f f i l t ers, a n d t h e de cima t i o n phas es a r e s e t t o 0 and 1. th e de cima t i o n phas es can b e s e t t o 0 fo r o n e cha n n e l, a n d 1 fo r t h e s e con d chann e l in t h e p a ir . this ca us es t h e f i rst cha n n e l t o p r o d uce t h e e v e n o u t p u t s, and t h e s e con d t o p r o d uce t h e o d d output s of t h e f i lte r . t h e st re am s c a n t h e n b e re c ombi n e d (in t erle a v e d ) t o p r o d uce t h e des i r e d 10 mh z o u t p u t r a t e . the b e nef i t is t h a t now e a ch chan nel s rcf has t i me to c a l c u l a t e t w ice as man y t a ps, b e ca us e i t has a lo w e r o u t p u t ra t e . stream control complex filter completion parallel port a parallel port c parallel port b agc0 agc0 str0 ch0 agc1 agc1 str1 ch1 agc2 agc2 str2 ch2 agc3 agc3 str3 ch3 agc4 agc4 str4 ch4 agc5 agc5 str5 ch5 04998-0-038 f i gure 38. o u tput d a t a rou t er bl ock d i agr a m
AD6636 rev. 0 | page 38 of 72 the interleaving function is a simple time-multiplexing function, with lower data rate on the input side and higher data rate on the output side. the output data rate is the sum of all input stream data rates that are combined. the channels that need to be combined are programmable with sufficient flexibility. table 22 gives the combinations that are possible using a 4-bit word (stream control bits) in the parallel port control 2 register. after interleaving of data (see the output data router section), the data is passed to the second subblock, in which either complex filter completion or biphase filtering can be performed. complex filter completion in normal operation, each individual channels filter performs real coefficient, complex data filtering. two channels are used to perform complex coefficient data filtering. one channel is loaded with the real part (in-phase) of the coefficients; the other channel is loaded with the imaginary part (quadrature) of the coefficients. the terms calculated are as follows: ? (ici, qci) from first channel ? (icq, qcq) from the second channel using these terms, the complex filter is completed by applying the following formula: ( i + jq ) (ci + jcq ) = ( ici ? qcq ) + j ( icq + qci ) the channels to be combined can be programmed using a 3-bit complex control word in the parallel output control 2 register. the values for the 3-bit control word and the corresponding settings are listed in table 23. these outputs go to the six available agcs. not all agcs need to be used in the different applications, so unused agcs can be bypassed and the output data streams ignored by the parallel output ports. for example, if streams 0 and 1 are combined for a complex filter, agc 1 can be bypassed, because stream 1 is already combined into stream 0 and sent to agc 0. table 22. stream control bit combinations stream control bits output streams no. of streams 0000 ch 0/1 combined, ch 2, ch 3, ch 4, ch 5 independent 5 0001 ch 0/1/2 combined, ch 3, ch 4, ch5 independent 4 0010 ch 0/1/2/3 combined; ch 4, ch 5 independent 3 0011 ch 0/1/2/3/4 combined; ch 5 independent 2 0100 ch 0/1/2/3/4/5 combined 1 0101 ch 0/1/2 combined, ch 3/4/5 combined 2 0110 ch 0/1 combined, ch 2/3 co mbined, ch 4/5 combined 3 0111 ch 0/1 combined, ch 2/3 combin ed, ch 4, ch 5 independent 3 1000 ch 0/1/2 combined, ch 3/4 combined, ch 5 independent 3 1001 ch 0/1/2/3 combined , ch 4/5 combined. 2 any other state independent channels 6 table 23. definitions for complex control register selections complex control word data routing comments 000 no complex filters stream control register controls agc usage. 001 stream 0/1 combined allows ch 0 an d ch 1 to form a complex filter. 010 stream 0/1 combined, stream 2/3 combined allows ch 0 and ch 1 to form a co mplex filter and ch 2 and ch 3 to form a complex filter. 011 stream 0/1 combined, stream 2/3 combined, stream 4/5 combined allows ch 0 and ch 1 to form a comp lex filter, ch 2 and ch 3 to form a complex filte,r and ch 4 and ch 5 to form a complex filter. 101 stream 0/1 combined allows ch 0 an d ch 1 to form a biphase filter. 110 stream 0/1 combined, stream 2/3 combined allows ch 0 and ch 1 to form a bi phase filter, and ch 2 and ch 3 to form a biphase filter. 111 stream 0/1 combined, stream 2/3 combined, stream 4/5 combined allows ch 0 and ch 1 to form a biph ase filter, ch 2 and ch 3 to form a biphase filter, and ch 4 and ch 5 to form a biphase filter.
AD6636 rev. 0 | page 39 of 72 biphase filtering option the second special function that can be performed by the second subblock of the output data router is called the biphase filtering option. with this option, the AD6636 can be used to process data from adcs that run faster than the input clock frequency by using two channels or two streams to form a biphase filter. for example, a 300 mhz adc can be used with a clock rate of 150 mhz driving the adc. the adc data can be decimated by 2 to produce even and odd data streams of data. the even stream can be clocked into adc input port a, and the odd stream can be clocked into adc input port b. these input ports drive separate channels or separate groups of channels. the filters of the rcf can be designed to place a 300 mhz sample time difference (1/300 mhz = 3.3 ns) between the even and odd path filters. after the channel-filter coefficients have appropriate delay, a complex addition of the odd and even sample channels can be performed to create a single filter. this equivalent filter looks like a single channel with a 300 mhz input rate, even though the clock rate of the chip runs at only 150 mhz. a biphase filter summation is implemented by the following equation: output = ( ie ce + io co ) + j ( qe ce + qo co ) where: ie ce , qe ce are even in-phase and quadrature-phase samples from one stream. io co and qo co are odd in-phase and quadrature-phase samples from the other stream. ce and co are the even and odd coefficients, which differ by 1 high speed sample time (300 mhz in the previous example). users can program certain streams to be summed using the biphase filtering option. this option can be programmed using the same 3-bit complex control word in the parallel output control 2 register. the values for the 3-bit control word and their corresponding settings are listed in table 23. automatic gain control the AD6636 is equipped with si x independent automatic gain control (agc) loops that directly follow the second data router and immediately precede the parallel output ports. each agc circuit has 96 db of range. it is important that the decimating filters of the AD6636 preceding the agc reject unwanted signals, so that each agc loop is operating only on the carrier of interest, and carriers at other frequencies do not affect the ranging of the loop. the agc compresses the 24-bit complex output from the second data router into a programmable word size of 4 to 8, 10, 12, or 16 bits. because the small signals from the lower bits are pushed in to higher bits by a dding gain, the clipping of the lower bits does not compromise the snr of the signal of interest. the agc maintains a constant mean power on the output despite the level of the signal of interest, allowing operation in environments where the dynamic range of the signal exceeds the dynamic range of the output resolution. the output width of the agc is set by writing a 3-bit agc word length word in the agc control register of the individual channels memory map. the agc can be bypassed, if needed, and, when bypassed, the 24-bit complex input word is still truncated to a 16-bit value that is output through the parallel port output. the six agcs available on the AD6636 are programmable through the six channel memory maps. agcs corresponding to individual channels can be bypassed by writing logic 1 to agc bypass bit in the agc control register. three sources of error can be introduced by the agc function: underflow, overflow, and modulation. underflow is caused by truncation of bits below the output range. overflow is caused by clipping errors when the output signal exceeds the output range. modulation error occurs when the output gain varies while receiving data. the desired signal level should be set based on the probability density function of the signal, so that the errors due to under- flow and overflow are balanced. the gain and damping values of the loop filter should be set, so that the agc is fast enough to track long-term amplitude variations of the signal that might cause excessive underflow or overflow, but slow enough to avoid excessive loss of amplitude information due to the modulation of the signal. agc loop the agc loop is implemented using a log-linear architecture. it contains four basic operations: power calculation, error calcula- tion, loop filtering, and gain multiplication. the agc can be configured to operate in either desired signal level mode or desired clipping level mode. the mode is set by the agc clipping error bit of the agc control register. the agc adjusts the gain of the incoming data according to how far it is from a given desired signal level or desired clipping level, depending on the selected mode of operation. two datapaths to the agc loop are provided: one before the clipping circuitry and one after the clipping circuitry, as shown in figure 39. for the desired signal level mode, only the i/q path from before the clipping is used. for the desired clipping level mode, the difference of the i/q signals from before and after the clipping circuitry is used.
AD6636 rev. 0 | page 40 of 72 i q 2 power of 2 p pole r desired i q clip 22 bits programmable bit width error k1 gain used only for desired clipping level mode gain multiplier k2 gain e error threshold k z C1 1 C (1 + p) z C1 + p z C2 square root average 1 ? 16384 samples decimate 1 ? 4096 samples log 2 (x) mean square (i 2 + q 2 ) clip 04998-0-039 f i g u re 39: bl ock d i ag r a m of t h e a g c d e sir e d signal l e v e l mode i n t h is m o de o f o p era t ion, t h e a g c st r i v e s t o ma in t a in t h e o u t p u t sig n al a t a p r og ra mma b l e s e t le ve l . th e desir e d sig n al lev e l m o de is s e l e c t ed b y wr i t ing l o g i c 0 in t o t h e a g c c l i p p i ng er r o r ena b le b i t o f t h e a g c con t r o l r e g i s t er . the lo o p f i n d s t h e sq ua r e (o r p o w e r) o f th e in co m i n g co m p lex da t a signal b y s q ua r i n g i and q a n d ad din g t h e m . the a g c lo o p has a n a v era g e and de cima te b l o c k. this a v era g e and de ci ma te op er a t ion t a k e s place on p o wer s a m p les an d b e f o re t h e s q u a re ro ot op e r a t i o n . t h i s bl o c k c a n b e pro - g r a m m e d t o a v era g e f r o m 1 t o 16,384 p o w e r s a m p les, a n d t h e de cim a te s e c t ion can b e p r o g r a mme d to up da te t h e a g c on ce ev er y 1 t o 4,096 s a m p les. th e limi t a tion o n t h e a v era g in g o p era t ion is t h a t t h e n u m b er o f a v era g e d p o w e r s a m p les sh o u ld b e a m u lt ipl e of t h e d e c i m a t i on v a lu e ( 1 , 2 , 3 , or 4 ) . the a v er a g in g and de cima t i on e f fe c t i v e l y m e an s t h a t t h e a g c ca n op era t e o v er a v era g e d p o w e r o f 1 t o 16,384 o u t p u t s a m p les. u p da t i n g t h e a g c o n ce e v er y 1 t o 4,096 s a m p les a n d o p era t ing o n a v e r a g e po w e r fa cili t a t e s t h e i m p l em en ta t i o n o f th e loo p f i l t er wi t h s l o w t i me co n s t a n t s, wher e t h e a g c er r o r co n v erg e s s l o w l y a n d ma k e s inf r e q uen t gain ad j u s t m e n t s. i t is als o us ef u l when t h e us er wa n t s t o k e ep t h e ga i n s c alin g co n s t a n t o v er a f r ame of d a t a or a st re am of s y mb o l s . d u e t o t h e li mi t a t i o n t h a t t h e n u m b er o f a v erag e s a m p les m u s t b e a m u lt ipl e of t h e d e c i m a t i on v a lu e, on ly t h e m u lt ipl e n u m b ers 1, 2, 3, o r 4 a r e p r og ra mmed . this is s e t usin g the a g c a v era g e s a m p les w o r d in t h e a g c a v era g e s a m p le r e g i s t er . th e s e a v era g e d s a m p les a r e t h e n de cima te d wi t h de cima t i on ra tios p r og ra mma b l e f r o m 1 t o 4,096. this decima tion ra tio is def i n e d i n t h e 1 2 -b i t a g c u p d a te de ci ma t i on reg i ster . the a v er a g e and de cima te o p er a t io n s a r e t i e d tog e t h er an d im ple m e n te d usin g a f i rst - o r der ci c f i l t er and f i f o r e g i sters. ga in an d b i t g r o w t h a r e ass o ci a t e d wi t h ci c f i l t ers an d de p e nd o n th e d e cim a tio n ra ti o . t o co m p en sa t e f o r th e g a i n as soci a t e d wi t h t h es e o p era t io n s , a t t e n u a t i o n s c a l in g is p r o v ide d b e fo r e t h e ci c f i l t er . this s c a l in g o p e r a t io n ac co un ts fo r t h e divisio n ass o c i a t e d w i t h t h e a v era g i n g op era t ion as we l l as t h e t r adi t io nal b i t g r o w t h in ci c f i l t ers. b e c a us e t h is s c a l ing is im ple m e n t e d as a b i t - sh if t o p era t ion, o n ly co a r s e s c a l in g is p o ssi b le . f i n e s c a l in g is im ple m e n t e d as a n o f fs et in t h e r e q u es t le v e l, as expla i n e d la t e r in t h is s e c t io n. the a t t e n u a t ion s c a l in g s ci c is pr o g r a mmable f r o m 0 t o 14 usi n g a 4-b i t ci c s c ale w o r d in t h e a g c a v er a g e sa m p l e s r e gi s t e r a n d i s gi v e n b y ( ) [ ] = 2 log wher e: m cic is t h e decima tion ra tio (1 t o 4,096). n av g is t h e n u m b er o f a v era g e d s a m p les p r og ra mme d as a m u l t i p le o f t h e d e cima tio n r a tio (1, 2, 3 , o r 4). f o r exa m p l e , if a d e cima tio n ra tio m cic is 1,000 a n d n av g is 3 (decima t io n o f 1,000 a n d a v erag in g o f 3,000 s a m p les), th en t h e ac t u al gain d u e t o a v era g in g and decima tion is 3,000 o r 69.54 d b (log 2 (3000)). b e ca us e a t t e n u a t io n is im p l emen t e d as a b i t- s h if t o p era t ion, o n l y m u l t i p les of 6.02 db a t t e n u a t io n s a r e pos s i b l e . s ci c in this cas e is 12, c o r r es p o n d in g t o 72.24 db . this wa y , s ci c s c a l in g a l wa ys a t t e n u a t es m o r e t h an is suf f icien t t o co m p e n s a t e fo r t h e ga i n i n t h e a v era g e an d de ci ma t e s e c t io n s a n d , t h er efo r e , pr e v en t s o v er f l o w s in t h e a g c l o o p . b u t i t is als o evi d en t th a t t h e s ci c s c aling i n d u ces a ga in er r o r (t h e dif f er en c e bet w een g a in d u e t o c i c a n d a t t e n u a t i o n p r o v id ed b y scali n g ) o f u p t o 6.02 db . this er r o r s h o u ld be com p en s a t e d f o r in t h e r e q u es t signal le v e l , as exp l a i n e d la t e r in this s e c t io n. a loga r i t h m t o t h e b a s e 2 is a p plie d t o t h e o u t p u t f r o m t h e a v era g e an d de c i ma te s e c t ion. th es e de cima t e d p o w e r s a m p les a r e co n v er t e d t o r m s sig n al s a m p les b y a p p l yin g a s q u a r e r o o t o p era t ion. this s q ua r e r o o t is i m ple m en t e d usi n g a si m p le shif t
AD6636 rev. 0 | page 41 of 72 o p e r a t i o n in th e log a ri th m i c d o ma in. the r m s s a m p les ob t a in e d a r e s u b t r ac t e d f r o m t h e r e q u es t sig n al le v e l r sp e c if ie d in t h e a g c d e s i re d l e vel re g i ste r , l e av i n g an e r ror te r m to b e pro c e s s e d by t h e l o op f i lt e r , g ( z ) . the us er s e ts t h is p r og ra mma b l e r e q u es t sig n al le v e l r acco r d - in g t o t h e o u t p u t signal lev e l tha t is desir e d . th e r e q u es t signal lev e l r is p r og ramma b l e f r o m ? 0 db t o ?23.99 db in s t eps o f 0.094 db . the r e q u es t sig n al le v e l s h o u l d als o co m p en s a te fo r er r o rs, if a n y , d u e t o t h e ci c s c aling, as expla i n e d p r e v i o us ly in t h is s e c t io n. th er efor e , t h e r e q u es t si g n al le v e l is o f fs et b y t h e amou n t of e r ror i n d u c e d i n c i c , g i ve n by off s e t = 10 log( m cic n av g ) ? s cic 3.01 db wher e off s e t is in db . c o n t in u i n g t h e p r e v io us exa m ple , t h is o f fs et is g i v e n b y off s e t = 72.24 ? 69.54 = 2.7 db s o t h e r e q u est sig n al le v e l is g i ven b y dbfs 094 . 0 094 . 0 ) ( ? ? ? ? ? ? ? ? = offset dsl ceil r wher e: r is t h e r e q u es t sig n al le v e l. ds l (desir ed sig n al lev e l) is t h e o u t p u t sig n al le v e l tha t t h e us er desir e s. ther efo r e , in t h e p r e v io us exa m ple , if t h e desir e d sig n al le ve l is ?13.8 db , th e r e q u es t leve l r is p r og ra mm e d t o be ?16.54 db , co m p en sa t i n g fo r th e o f fset. this r e q u es t sig n al lev e l is p r og ra mmed in t h e 8-b i t a g c d e s i re d l e v e l re g i ste r . t h i s re g i st e r h a s a f l o a t i ng - p oi n t re pre s e n - t a t i on, w h er e t h e 2 ms bs a r e ex p o n e n t b i ts and t h e 6 lsbs a r e ma n t is s a b i ts. th e exp o n e n t is i n s t eps o f 6.02 db , a n d t h e ma n t is s a is in s t eps o f 0.094 db . f o r exa m p l e , a val u e 10100101 r e p r es en ts 2 6 . 02 + 37 0.094 = 15.518 db . the a g c p r o v i d es a p r og ra mma b l e s e cond-or d er lo o p f i l t er . t h e p r ogra m m a b le pa ram e t e r s ga in 1 (k 1 ), ga in 2 (k 2 ), er r o r t h r e sh old e, and p o le p com p letely def i n e t h e l o o p f i l t er cha r ac t e r i s t ics. the er r o r t e r m a f t e r s u b t rac t ing t h e r e q u est sig n al le v e l is p r o c es s e d b y t h e l o o p f i l t er , g(z). the o p e n lo o p p o les o f t h e s e c o nd-o r d er lo o p f i l t er a r e 1 a n d p , r e s p e c t i v e ly . the lo o p f i l t er p a ra m e ters, p o le p an d ga in k, al lo w th e a d j u s t m e n t o f th e f i l t e r tim e co n s ta n t tha t d e t e rm i n e s t h e wi n d o w fo r calc u l a t i n g t h e p e a k -t o-a v era g e r a t i o . d e p e n d in g on t h e va l u e o f t h e er r o r t e r m t h a t is ob t a i n e d a f t e r s u b t r ac t i n g t h e r e q u es t sig n al le v e l f r o m t h e ac t u al sig n al le ve l, ei t h er ga in va l u e , k 1 or k 2 , is us e d . i f t h e er r o r i s les s t h a n t h e p r o g r a mmable t h r e sh old e, k 1 or k 2 is used . t h is al lo ws a fas t lo o p wh e n t h e e r r o r t e r m is hig h (la r g e con v erg e n c e s t eps re qu i r e d ) a n d a sl owe r l o op f u nc t i on w h e n e r ror te r m i s s m a l l e r (alm os t co n v er ged ) . t h e o p en - l oo p g a i n u s ed i n t h e seco n d - o r d e r loo p g ( z ) i s gi v e n by one of t h e f o l l ow i n g e q u a t i o n s : k = k 1 , if e r ror < er ror t h re sh o l d k = k 2 , if e r ror > er ror t h re sh o l d the o p e n -lo o p t r a n sfer f u n c t i on fo r t h e f i l t er , i n cl udin g t h e ga i n pa ra m e t e r , i s () () 2 1 1 1 1 ? ? ? + + ? = pz z p kz z g i f t h e a g c is p r o p erly co nf igur e d i n t e r m s o f o f fs et in r e q u es t le v e l, t h en t h er e a r e n o ga in s in t h e a g c lo o p e x cep t fo r t h e fi l t e r g a i n k . u n der t h es e c i r c um s t an ces, a clos e d -lo o p exp r es sio n fo r t h e a g c lo o p is g i v e n b y () () () () 2 1 1 1 1 1 ? ? ? + ? ? + = + = pz z p k kz z g z g z g closed the gai n p a r a meters k 1 , k 2 , an d p o le p a r e p r og ra mma b l e thr o ug h a g c l o o p ga in 1, 2, a n d a g c p o le lo c a tio n reg i s t ers f r o m 0 t o 0.996 in s t eps o f 0.0039 usin g 8-b i t r e p r es en t a tio n . f o r exa m p l e , 1000 1001 r e p r es en t (1 37/256 = 0.535156). th e er r o r thr e s h old va l u e is p r og ra mma b l e betw een 0 db a n d 96.3 db in s t eps o f 0.024 db . this val u e is p r og ra mm e d in th e 12-b i t a g c e r ror t h re sho l d re g i ste r , u s i ng f l o a t i ng - p oi n t re pre s e n t a t i on . i t co n s is ts o f fo ur exp o n e n t b i ts and eig h t man t iss a b i ts. e x p o n e n t b i ts a r e i n s t eps o f 6.02 db a n d ma n t is s a b i ts a r e in st eps o f 0.024 db . f o r exa m p l e , 0111100 01001 r e p r es en ts 7 6.02 + 137 0.024 = 45.428 db . the us er def i n e s t h e o p en-lo o p p o le p a n d ga i n k, which als o d i r e ctl y i m pa ct th e p l a c em en t o f th e c l osed - l oo p po le s a n d f i l t er char ac ter i st ic s . the s e cl o s e d -l o o p p o l e s , p 1 , p 2 , a r e t h e r o o t s o f t h e de n omina t o r o f t h e p r e v io us clos e d -lo o p t r a n sfer f u n c t i o n an d are g i ve n by 2 4 ) 1 ( ) 1 ( , 2 p k p k p p p 2 1 ? ? + + ? + = t y pi c a l l y , t h e a g c l o op p e r f or m a n c e i s d e f i ne d i n te r m s of it s ti m e co n s ta n t o r se t t li n g t i m e . i n th i s case , t h e closed - l oo p po le s s h o u ld be se t t o m eet th e tim e co n s ta n t s r e q u i r e d b y th e a g c lo o p .
AD6636 rev. 0 | page 42 of 72 t h e r e la ti o n s h i p be tw een th e tim e co n s t a n t a n d th e c l osed - l oo p po le s th a t ca n be u s ed f o r th i s p u r p ose i s ? ? ? ? ? ? ? ? = 2 1, cic 2 1, rate sample m p exp w h er e a r e t h e t i m e con s t a n t s cor r es p o n d i n g t o p o les p 1, 2 . 2 1 , the t i m e con s t a n t s c a n a l s o b e der i ve d f r o m s e t t lin g t i m e s as gi v e n b y 3 % 5 4 % 2 time settling or time settling = m ci c (ci c decima tion is f r o m 1 t o 4,096), a n d ei ther th e s e t t lin g ti m e o r tim e co n s ta n t a r e ch osen b y th e u s e r . th e sa m p le ra t e is th e s a m p le ra t e o f th e s t r e am co min g in t o t h e a g c. i f c h a n n e ls w e r e i n t e r l ea v e d i n t h e o u t p u t da ta r o u t e r , th en th e co m b in e d s a m p le ra t e in t o th e a g c sh o u l d b e co n s ider e d . this ra te s h o u ld b e us ed in the calc u l a t ion o f p o les in t h e p r e v io us eq ua ti o n , w h e r e th e sa m p le ra t e i s m e n t i o n e d . the lo o p f i l t er ou t p ut co r r es p o nds t o t h e sig n a l ga in t h a t is u p da te d b y t h e a g c. b e c a us e a l l co m p u t a t ion i n t h e lo o p f i l t er is do ne in loga r i thmic do main ( t o th e b a s e 2) o f th e s a m p les, t h e sig n al gain i s g e n e r a t e d using t h e exp o n e n t (p o w er o f 2) o f t h e lo o p f i l t er ou t p ut. the ga i n m u l t i p lier g i v e s t h e p r o d uc t o f t h e sig n al ga in w i t h b o t h t h e i and q da t a e n ter i n g t h e a g c s e c t ion. this sig n a l ga in is a p plie d a s a co a r s e 4- b i t s c a l in g an d t h e n as a f i ne s c a l e 8-b i t m u lt i p lier . ther efo r e , t h e a p plie d sig n al gain is f r o m 0 t o 96.3 db in s t eps o f 0.024 db . the ini t ial sig n a l ga in is p r og ra m- ma b l e usin g t h e a g c sig n al ga in r e g i s t er . this reg i s t er is a g ain a 4 e x p o n e nt + 8 m a nt i s s a b i t f l o a t i n g - p o i nt r e p r e s e n t a t i o n simi la r t o t h e er r o r t h r e s h old . this is t a k e n as t h e i n i t ial ga i n va l u e b e fo r e t h e a g c lo o p st a r t s o p era t i n g. the p r o d uc ts o f t h e ga i n m u l t i p lier a r e t h e a g c s c ale d o u t p u t s wi t h a 19 -b i t r e p r es en t a t i o n . th es e a r e in t u r n us e d as i and q fo r calc u l a t in g t h e p o w e r , a n d t h e a g c er r o r a nd lo o p a r e f i l t er e d t o p r o d uce t h e sig n al g a in fo r t h e n e xt s e t o f s a m p les. th es e a g c s c al ed o u t p u t s can be p r og ra mm e d t o ha v e 4-, 5-, 6-, 7-, 8-, 10-, 12-, o r 16-b i t wid t h s b y usin g th e a g c o u t p u t word l e ng t h wo rd i n t h e a g c c o n t ro l re g i ste r . t h e a g c s c a l e d o u t p u t s a r e tr u n ca t e d t o th e r e q u i r ed b i t w i d t h s b y u s i n g th e c l i p p i ng cir c ui tr y , as s h o w n in f i gur e 39. a v e r a g e sa m p le s se t t i n g th o u g h i t is com p lic a t e d t o ex p r es s t h e exac t e f fe c t o f t h e n u m b er o f a v era g in g s a m p les b y usin g e q ua t i on s, in t u i t i v e l y i t has a s m o o t h i n g ef fe c t o n t h e wa y t h e a g c lo o p addr es s e s a s u dden in cr eas e o r a s p i k e in t h e sig n al lev e l . i f a v era g in g o f f o ur sa m p le s i s used , th e a g c ad d r e s se s a s u d d e n in cr ea se i n sig n al lev e l m o r e s l o w l y co m p a r ed t o n o a v er a g in g. th e s a m e a p plies to t h e m a nner in w h ich t h e a g c ad dr ess e s a sudde n le s r e 3 9 ; t h e o p er a t io n e r r ror c e o f n er r o r t e r m t o b e p r o c es s e d b y t h e s e cond- h e d i s s i r e d l e v e l r e g i s t ers in st e a d o f in t h e op c e d b y s e t t in g t h e a p p r o p r i a t e b i ts o f t h e a g c c o n t ro l re g i ste r . ? nch r on i z e t h e s y nc now bit : t h rou g h t h e a g c c o n t ro l re g i st e r . d e c r ea se in t h e s i gn al l e v e l . d e sired clip pi ng l e v e l mo de e a c h a g c can be co nf igur e d s o tha t the lo o p lo c k s o n t o a desir e d cli p p i n g le vel o r a desir e d sig n a l le vel. d e sir e d cli p pin g l e v e l m o de i s se lect ed b y w r i t i n g logi c 1 i n t h e a g c c l i p p i n g e r ror mo d e bit i n t h e a g c c o n t ro l re g i ste r . f o r s i g n a l s t h a t te n d t o exce e d t h e b o un ds o f t h e p e ak-t o- a v er a g e r a t i o , t h e desir e d c l ippi n g l e v e l o p t i on prov i d e s a w a y to pre v e n t t r u n c a t i ng t h o s e sig n als a nd s t il l p r o v ide an a g c t h a t a t t a c k s q u ic kl y an d s e t t t o th e desir e d o u t p u t lev e l . th e sig n al p a th f o r this m o de o f o p er a t ion is sh o w n w i t h do tte d lin e s i n f i g u is simila r t o t h e desir e d sig n al le v e l m o de . f i rs t, t h e da t a f r o m t h e ga i n m u l t i p lier is t r un c a t e d t o a lo w r e s o l u tio n (4, 5, 6, 7, 8, 10, 12 , o r 16 b i ts) as s e t b y th e a g c output word l e n g t h word i n t h e a g c c o n t ro l re g i ste r . a n e ter m ( f o r b o t h i a nd q) is gener a te d t h a t is t h e dif f er en ce be tw e e n t h e sig n als befo r e an d a f t e r t r un c a t i on. this t e r m is p a s s e d t o t h e com p lex s q ua r e d ma g n i t ude b l o c k, fo r a v era g in g a nd de ci ma t i n g t h e up da te s a m p les a nd t a k i n g t h eir s q ua r e r o o t t o f i n d r m s s a m p les as in desir e d sig n al le ve l mo de . i n p l a t h e r e q u est desi r e d sig n a l le vel, a desir e d cl i p p i n g le vel is s u b t rac t e d , le a v i n g a ord e r l o op f i lte r . the r e s t o f t h e lo o p o p era t es t h e s a m e w a y as t h e desir e d sig n a l lev e l m o de . t h is w a y , th e tr u n ca ti o n e r r o r i s calcula t e d a n d t a g c loo p o p e r a t e s t o m a i n ta in a co n s t a n t tr u n ca ti o n e r r o r le v e l. th e only r e g i s t er s e t t ing t h a t is dif f er en t f r o m t h e desir e sig n al lev e l m o de s e t t in gs is tha t t h e desir e d c l i p p i n g leve l s t o r e d in t h e a g c d e re qu e s t s i g n a l l e vel. a g c s y nch r oni z ation w h en t h e a g c o u t p ut is co nn e c t e d t o a r a ke r e cei v er , t h e r a ke r e cei v er ca n s y n c hr o n i z e t h e a v era g e and u p da t e s e c t ion t o u p da te t h e a v era g e p o w e r fo r a g c er r o r calcu l a t ion an d lo f i l t er in g. this e x t e r n al syn c sig n al sy n c hr o n ize s t h e a g c cha n g e s t o t h e r a ke r e cei v er a nd ma k e s s u r e t h a t t h e a g ga in w o r d do es n o t cha n g e o v er a sy m b ol p e r i o d , w h ich, t h er efo r e , p r o v ides a m o r e acc u ra t e es t i ma t i o n . this sy n c hr o - niza tion can be acco m p l i s h sy n c s e l e c t a l t e r n a t i v e s the a g c can r e cei v e a sy n c as fol l o w s: c h an nel s y nc : t h e s y nc s i g n a l i s u s e d to s y n c o o f t h e channel u n der co n s ider a t ion. ? pi n s y nc : s e l e c t one of t h e f o u r s y n c pi ns . ?
AD6636 rev. 0 | page 43 of 72 w h en t h e c h ann e l sy n c s e lec t b i t o f th e a g c c o n t r o l r e g i s t er is l o g i c 1, t h e a g c r e cei v es t h e s y n c sig n al us e d b y t h e n c o of t h e co r r es p o n d i n g cha n n e l fo r t h e st a r t. w h en t h is b i t is l o g i c 0 , t h e pin s y n c def i n e d b y t h e 2- b i t s y nc p i n s e le c t w o r d in t h e a g c co n t r o l r e g i s t er is us e d t o p r o v ide t h e sy nc t o t h e a g c. a p a r t f r o m t h es e tw o m e t h o d s, t h e a g c co n t r o l r e g i s t er als o has a sy n c n o w b i t t h a t can b e us e d t o p r o v ide a syn c t o t h e a g c b y w r i t in g t o th i s r e gi s t e r th r o u g h th e m i cr o p o r t o r se ri al po r t . p a r a llel port output the AD6636 inco r p o r a t es thr e e indep e nden t 1 6 -b i t p a ral l e l po r t s f o r o u t p u t da ta tra n s f e r . t h e th r e e pa ralle l o u t p u t po r t s s h a r e a co mm o n c l o c k, pclk. e a c h p o r t co n s is ts o f a 16-b i t da t a b u s, req u es t sig n al , a c kn o w le dge sig n al, t h r e e c h a n n e l indic a to r p i n s , o n e i / q i n di ca to r p i n, on e ga i n wo r d indic a to r p i n, and a co m m on sha r e d pc lk p i n. t h e p a r a l l el p o r t s can b e co nf igur ed t o f u n c tio n in mast er m o de o r sla v e m o de . b y defa u l t, t h e p a ra l l e l p o r t s a r e in s l a v e m o de on p o w e r - u p . s y n c p r o c ess e a ch p a r a l l el p o r t c a n output d a t a f r om a n y or a l l of t h e a g c s , u s i n g t h e 1 - bi t e n abl e bi t for e a c h a g c i n t h e p a r a l l el p o r t co n t r o l r e g i s t er . e v en w h e n t h e a g c is n o t r e quir e d fo r a cer t a i n cha n nel, t h e a g c can b e b y p a ss e d , b u t t h e d a t a is st i l l r e c e i v ed f r o m th e b y pa s s ed a g c . t h e pa rall e l po r t fu n c ti o n ali t y i s p r ogra m m a b l e th r o u g h th e tw o pa ralle l po r t co n t r o l r e gi s t e r s . rega r d les s o f ho w a sy n c sig n al is r e cei v e d , t h e syn c in g p r o c ess is t h e s a me . w h en a s y n c is r e c e i v e d , a st a r t h o ld-o f f co un t e r is lo ade d w i t h t h e 16-b i t val u e i n t h e a g c h o ld-o f f r e g i s t er , w h ich i n i t i a te s t h e c o u n tdown. t h e c o u n tdow n i s b a s e d on t h e a d c in p u t clo c k. w h en t h e co un t r e a c h e s 1, a sy n c is ini t i a t e d . w h en a sy n c is ini t ia t e d , t h e ci c de ci ma t i on f i l t er d u m p s t h e c u r r en t val u e t o t h e s q u a r e r o o t , er r o r e s t i ma t i o n , and lo o p f i l t er b l o c ks . af t e r d u m p in g t h e c u r r en t val u e , i t s t a r ts w o rki n g t o wa r d t h e n e xt u p da te val u e . a d di ti o n all y o n a sy n c , a g c ca n be ini t ia li ze d if t h e ini t ia li ze a g c o n sy n c b i t is s e t in t h e a g c co n t r o l r e g i st er . d u r i n g ini t ia li z a t i o n , t h e c i c a c c u m u l a t o r is cle a r e d an d ne w va l u es fo r ci c de cim a t i o n , n u m b er o f a v era g in g s a m p les, ci c s c ale , sig n al ga in, o p e n -lo o p ga in s k 1 a nd k 2 , an d po le pa ra m e t e r p ar e lo ad ed f r o m th eir r e s p ecti v e r e g i s t ers. w h en t h e i n i t iali ze o n syn c b i t is cle a r e d , t h e s e p a ra m e ters a r e n o t lo ade d f r o m t h e r e g i s t ers. e a ch p a r a l l el p o r t ca n b e p r o g r a mme d i ndivi d u a l ly to o p er a t e in ei t h er in t e rle a v e d i/q m o de o r p a ral l e l i/q m o de . th e m o de is s e le c t e d usin g a 1-b i t d a t a fo r m a t b i t in t h e p a ra l l e l p o r t c o n t ro l re g i ste r . i n b o t h mo d e s , t h e a g c g a i n w o rd output c a n be e n a b l e d u s i n g a 1 - b i t a p pen d g a i n b i t in th e pa rall e l po r t co n t r o l r e g i s t er fo r in divi d u al ou t p ut p o r t s. th e r e a r e six ena b le b i t s pe r o u t p u t po r t , o n e f o r eac h a g c in th e co rr e s po n d in g pa rall e l po r t . inte rleav e d i/ q mo de p a ral l e l p o r t c h a nne l m o de is s e lec t e d b y wr i t in g a 0 t o t h e da t a fo r m a t b i t fo r t h e p a ra l l e l p o r t in co n s ider a t ion. i n t h is m o d e , i an d q word s f r om t h e a g c are output on t h e s a m e 1 6 - bit d a t a b u s o n a t i m e -m u l t i p l exe d b a sis. th e 16 -b i t i w o r d is o u t p u t fol l o w e d b y t h e 16-b i t q w o r d . the s p e c if ic a g cs o u t p u t b y t h e p o r t a r e s e lec t e d b y s e t t in g individ u al b i ts f o r eac h o f th e a g cs i n t h e p a r a l l el p o r t c o n t ro l re g i ste r . f i g u re 4 0 sh ow s t h e t i m i ng d i a g ra m f o r th e in t e r l e a v e d i/q m o de . this sy n c p r o c e s s is a l s o ini t i a t e d w h e n a chan ne l com e s o u t o f s l e e p b y usin g t h e st a r t sy n c t o t h e n c o . an addi t i o n al fe a t ur e is t h e f i rst s y n c o n ly b i t in t h e a g c co n t r o l r e g i st er . w h e n t h is b i t is s e t, o n ly t h e f i rs t s y n c ini t ia t e s t h e p r o c es s a nd t h e r e ma inin g sy n c sig n a l s a r e ig n o r e d . this is us ef u l w h e n sy n c ing usin g a p i n sy n c . a sy n c is r e q u ir e d o n l y o n t h e f i rs t p u ls e o n t h is p i n. t h e s e a ddi t i ona l fe a t ur es ma k e a g c s y n c hr o n iz a t ion m o r e f l exi b le and a p p l ica b le t o va r i ed cir c um s t a n ces . pclkn t dpreq pxreq pxack t dpp px [15:0] i [15:0] q [15:0] pxiq t dpic pxch [2:0] pxch [2:0] = channel no. t dpch pxgain logic low ? 0 ? 04998-0-040 f i gure 40. inte rl eav e d i/q mode w i tho u t an a g c g a in w o r d
AD6636 rev. 0 | page 44 of 72 w h en an o u t p u t da t a s a m p le is a v a i la b l e f o r o u t p u t f r o m a n a g c , th e pa ralle l po r t i n i t ia t e s th e tra n s f e r b y p u lli n g th e p x r e q s i gn al h i gh . i n r e s p o n s e , th e p r oc e s so r r e c e i v i n g t h e da ta n e ed s t o p u ll th e p x a c k si gn al h i g h , a c kn o w led g i n g tha t i t i s re a d y to re c e i v e t h e s i g n a l . i n f i g u re 4 0 , p x a c k i s a l re a d y p u l l ed hig h an d , th er ef o r e , th e 1 6 -b i t i da ta is o u t p u t o n t h e da t a b u s o n t h e n e xt pclk r i sin g e d g e a f t e r pxreq is dr i v en log i c hig h . th e pxi q sig n al als o g o es hig h t o indic a te tha t i da ta is a v a i la b l e on t h e da t a b u s. th e next pclk c y cle b r in gs t h e q da ta o n t o t h e da ta b u s. i n this c y c l e , th e pxi q sig n al is dr i v en lo w . w h e n i d a t a an d q d a t a a r e o u t p ut, t h e ch a nnel i ndic a to r p i n s pxch[2:0] indic a t e t h e da t a s o ur ce (a gc n u m b er). f i g u r e 40 i s th e ti m i n g di a g ra m f o r i n t e r l ea v e d i/ q m o d e w i t h t h e a g c ga in wo r d dis a b l e d . f i gur e 41 is a simi la r t i min g di a g r a m w i t h t h e a g c ga i n w o rd . i a nd q da t a a r e as ex pla i n e d fo r f i gur e 40. i n t h e pc lk c y cle a f t e r t h e q da t a , t h e a g c gain w o r d is o u t p u t o n the da t a b u s a nd t h e pxgai n sig n al is p u l l e d hig h t o indic a te tha t t h e ga in wo r d is a v a i la b l e o n the p a ral l e l p o r t . th er efo r e , a minim u m o f t h r e e o r fo ur pclk c y cles a r e re qu i r e d to output o n e s a m p l e of output d a t a o n t h e p a r a l l el po rt w i th o u t o r w i th th e a g c g a i n w o r d , r e s p ect i v e l y . p a r a llel iq mo de i n t h is m o de , ei g h t b i ts o f i da t a an d e i g h t b i ts o f q da t a a r e output on t h e d a t a bu s s i m u lt a n e o u s ly d u r i ng one p c l k c y cl e . the i b y t e is t h e m o s t sig n if ican t b y t e o f t h e p o r t , w h i l e t h e q b y t e is t h e le ast sig n if ica n t b y t e . the p a i q and pbi q o u t p u t indic a t o r p i n s ar e s e t hig h d u r i n g th e pclk c y c l e . n o t e tha t if d a t a f r om m u l t ipl e a g cs are ou t p ut c o ns e c ut ively , t h e p a i q a nd pbi q o u t p u t i n di ca to r p i ns r e ma in h i g h u n t i l da t a f r o m a l l chan nel s is out p u t . the p a ch[2:0] a nd p b ch[2:0] p i n s p r o v ide a 3-b i t b i na r y val u e i n di ca t i n g t h e s o ur ce (a g c n u m b er) o f t h e da t a c u r r en t l y bein g o u t p u t . f i gur e 42 is th e tim i n g dia g ra m fo r pa ralle l i/q mo d e . pc l k n t dpreq px r e q px a c k t dpp p x [1 5: 0] i[1 5 : 0 ] q [1 5: 0] px i q t dpiq px c h [ 2 : 0 ] p x ch [ 2 : 0 ] = c h a n ne l # t dpch g a i n [1 1: 0] + 00 00 px g a i n t dpgain 04998-0-041 f i gure 41. inte rl eav e d i/q mode w i th a n a g c g a in w o r d
AD6636 rev. 0 | page 45 of 72 pxch [2:0] pclkn t dpreq pxreq pxack t dpp px [15:0] i [15:8] q [7:0] pxiq t dpiq pxch [2:0] = agc no. t dpch pxgain logic low 0 04998-0-042 f i gure 4 2 . p a r a ll el i/ q mo d e wi tho u t an a g c g a i n w o r d w h en an o u t p u t da t a s a m p le is a v a i la b l e f o r o u t p u t f r o m a n a g c , th e pa ralle l po r t i n i t ia t e s th e tra n s f e r b y p u lli n g th e p x r e q s i gn al h i gh . i n r e s p o n s e , th e p r oc e s so r r e c e i v i n g t h e da ta n e ed s t o p u ll th e p x a c k si gn al h i g h , a c kn o w led g i n g tha t i t i s re a d y to re c e i v e t h e s i g n a l . i n f i g u re 4 2 , t h e p x a c k i s a l re a d y p u lled h i g h a n d , th e r e f o r e , th e 8- b i t i d a ta a n d 8- b i t q d a ta a r e s i m u lt a n e o u s ly output on t h e d a t a bu s on t h e n e x t p c l k r i s i ng ed g e a f t e r p x r e q i s d r i v e n l o gi c h i gh . th e p x i q s i gn al al so g o es hig h t o indica t e tha t i/q da ta is a v a i lab l e o n the da t a b u s. w h en i/q da t a is bein g o u t p u t , th e c h ann e l indica t o r p i n s pxch[2:0] in dica te t h e da ta s o ur ce (a gc n u m b er). f i g u r e 42 i s th e ti m i n g di a g ra m f o r i n t e r l ea v e d i/ q m o d e w i t h t h e a g c ga in wo r d dis a b l e d . f i gur e 43 is a simi la r t i min g d i ag r a m w i t h t h e a g c g a i n word e n abl e d. i a n d q d a t a are a s s h o w n in f i g u r e 39. i n th e p c lk c y c l e a f t e r th e i/ q da t a , th e a g c ga in w o r d is o u t p u t o n t h e da t a b u s, an d t h e pxgain sig n al is p u l l ed hig h t o indic a te tha t t h e ga in wo r d is a v a i la b l e o n the p a ral l e l p o r t . dur i n g this pclk c y c l e , th e pxi q sig n al is p u l l ed lo w t o indic a t e tha t i/q da ta is n o t a v ail a b l e o n t h e da ta b u s. ther efo r e, in p a r a l l el i/q mo de, a mi ni m u m o f two pcl k c y c l es is r e q u ir ed t o o u t p u t o n e s a m p le o f o u t p u t da t a o n t h e pa rall e l po r t w i th o u t a n d wi th th e a g c g a in w o r d , r e s p ecti v e l y . the o r der o f da ta o u t p u t is dep e n d en t o n w h en da ta a r r i v e s a t th e po r t , w h i c h i s a fu n c ti o n o f t o tal d e cim a t i o n ra t e , d r c f / cr cf de cima t i o n phas e , a nd st a r t h o ld-o f f va lues. p r io r i ty o r der f r o m hig h es t t o lo w e s t is, a g cs 0, 1, 2, 3, 4, a n d 5 f o r bo t h p a ral l e l i/q a n d in t e rle a v e d m o des o f o u t p u t . mast er/sla v e pclk mo des the p a ral l e l p o r t s can o p era t e i n ei t h er mas t er o r s l a v e m o de . the m o de is s e t vi a pc lk mas t er m o de b i t i n t h e p a ral l e l p o r t c o n t r o l 2 r e gi s t e r . t h e pa rall e l po r t s po w e r u p i n s l a v e m o d e t o a v o i d pos s i b l e co n t en ti o n s o n th e pc l k p i n . i n ma ster m o d e , pclk is an o u tp u t der i ve d b y dividi n g pll_cl k do w n b y t h e p c lk divis o r . the pc lk divis o r ca n ha v e a val u e o f 1, 2, 4, o r 8 , dep e ndin g o n t h e 2 - b i t pclk di vis o r w o r d s e t t in g i n t h e p a ral l e l p o r t c o n t r o l 2 r e g i s t er . th e hig h es t p l ck r a t e in mas t er m o de is 200 mh z. m a s t er m o de is s e lec t e d b y s e t t in g t h e p c lk mas t er m o de b i t i n t h e p a ral l e l p o r t c o n t ro l 2 re g i st e r . divisor pclk rate clk pll rate pclk _ = i n sla v e mo de , e x t e r n al cir c ui t r y p r o v ides t h e p c lk sig n al. s l a v e - m o de p c lk sig n als can be e i t h er sy n c hro n o u s o r asy n chr o n o us. the max i m u m sla v e m o de p c l k f r e q uen c y is als o 200 mh z.
AD6636 rev. 0 | page 46 of 72 pclk t dpreq pxreq pxack t dpp px [15:0] i [15:8] q [15:8] pxiq t dpiq pxch [2:0] pxch [2:0] = channel # t dpch gain [11:0] + 0000 pxgain t dpgain 04998-0-043 f i gure 43. p a r a l l e l i / q mod e w i th an a g c g a i n w o r d p a r a llel p o r t pi n f u nc ti ons t a b l e 24 d e scri b e s th e fun c ti o n s o f th e p i n s u s e d b y th e pa ralle l po r t s . table 24. parallel port pin fu nctions pin name i/o function p c l k i / o pclk can operat e as a master or as a slave. this setting is dependent on the 1-bit pc lk master mode bit in the paralle l port control 2 register. as an output (m aster mode), the max imum frequency is clk/n, where clk is AD6636 clock and n is an integer divisor of 1, 2, 4, or 8. as an input (slave mode), it can be asynchronous or synchronous relative to the ad6 636 clk. this pin power s up as an input to avoi d possible conte n tions. paralle l port output pins change on the rising edge of pclk. pareq, pbreq, pcreq o active high output. synchronous to pclk. a logic high on this pin indicates that data is available to be shifted out of the port. when an ackn ow ledge signal is re cei ved, data starts shifting out and this pin remains high until all pending data has been shifted out. paack, pback, pcack i active high asynchronous inpu t. applying a log i c low on this pin inhibits parallel port data shifting. applying a logic high to this pin when req is high causes the parallel port to shift out data according to the programmed data mode. ack is sampled on the rising edge of pclk. assuming that req is asserted, the latency from the assertion of ack to data appeari n g at the paralle l port o utput is no more than 1.5 pclk cycles . ack can be he ld high continuou sly; in this case, whe n data becomes availa ble, shifting begins 1 pclk cycle afte r the assertion of req (see figure 40, figure 41, figur e 42, and figure 43). paiq, pbiq, pciq high whenever i data is present on the para lle l p o rt data bus; otherwise low. in parallel i/q mod e , both i data and q data are avail a ble at the sam e time and, therefore, the pxiq signal is pulled hi gh. pagain, pbgain, pcgain high whenever the agc gain word is present o n the parallel p o r t data bus; otherwise low. pach[2:0], pbch[2:0], pcch[2:0] these pins ident i fy data in both of the parallel p o rt modes. the 3-bit value id entifies the source of the data (ag c number) on the parallel p o rt wh en it is being shi f ted out. padata [ 15:0], pbdata[15:0 ] , pcdata [15:0] parallel output port data bus. output format is t w os comple me nt. in parall el i/ q mode, 8-bit data is prese n t; in interleaved i/q mode, 16-bit data is available.
AD6636 rev. 0 | page 47 of 72 user-configurable built-in self-test (bist) each channel of AD6636 includes a bist block. the bist, along with an internal test signal (pseudorandom test input signal), can be used to generate a signature. this signature can be compared with a known good devi ce and an untested device to see if the untested device is functional. bist timer bits in the bist control register can be programmed with a timer value that determines the number of clock cycles that the output of the channels (output of agc) have accumulated. when the disable signature generation bit is written with logic 0, the bist timer is counted down and a signature register is written with the accumulated output of the AD6636 channel. when the bist timer expires, the signature register for i and q paths can be read back to compare it with the signature register from a known good device. chip synchronization the AD6636 offers two types of synchronization: start sync and hop sync. start sync is used to bring individual channels out of sleep after programming. it can also be used while AD6636 is operational to resynchronize the internal clocks. hop sync is used to change or update the nco frequency tuning word and the nco phase offset word. two methods can be used to initiate a start sync or hop sync: ? soft sync is provided by the memory map registers and is applied to channels directly through the microport or serial port interface. ? pin sync is provided using four hard-wired sync[3:0] pins. each channel is programmed to listen to one of these sync pins and do a start sync or a hop sync when a signal is received on these pins. the pin synchronization configuration register (address 0x04) is used to make pin synchronization even more flexible. the part can be programmed to be edge-sensitive or level-sensitive for sync pins. in edge-sensitive mode, a rising edge on the sync pins is recognized as a synchronization event. start start refers to the startup of an individual channel or chip, or of multiple chips. if a channel is not used, it should be put into sleep mode to reduce power dissipation. following a hard reset (low pulse on the reset pin), all channels are placed into sleep mode. alternatively, channels can be put to sleep manually by writing 0 to the sleep register. start with soft sync the AD6636 can synchronize channels or chips under micro- processor control. the start hold-off counter, in conjunction with the soft start enable bit and the channel enable bits, enables this synchronization. to synchronize the start of multiple channels via micro- processor control: 1. write the channel enable register to enable one or more channels, if the channels are inactive. 2. write the nco start hold-off counter(s) to the appropriate value (greater than 1 and less than 2 16 ). 3. write the soft sync channel enable bit(s) and soft start synchronization enable bit high in the soft synchronization configuration register. this starts the countdown by the start hold-off counter. when the count reaches 1, the channels are activated or resynchronized. start with pin sync four sync pins (0, 1, 2, and 3) provide very accurate synchro- nization among channels. each channel can be programmed to monitor any of the four sync pins. to start the channels with a pin sync: 1. write the channel register to enable one more channels, if the channels are inactive. 2. write the nco start hold-off counter(s) to the appropriate value (greater than 1 and less than 2 16 ? 1). 3. program the channel nco control registers to monitor the appropriate sync pins. 4. write the start synchronization enable bit and sync pin enable bits high in the pin synchronization configuration register. this starts the countdown of the start hold-off counter. when the count reaches 1, the channels are activated or resynchronized. hop hop is a jump from one nco frequency and/or phase offset to a new nco frequency and/or phase offset. this change in frequency and/or phase offset can be synchronized via microprocessor control (soft sync) or via an external sync signal (pin sync).
AD6636 rev. 0 | page 48 of 72 hop with soft sync the AD6636 can synchronize a change in nco frequency and/or phase offset of multiple channels or chips under microprocessor control. the nco hop hold-off counter, in conjunction with the soft hop enable bit and the channel enable bits, enables this synchronization. to synchronize the hop of multiple channels via microprocessor control: 1. write the nco frequency register(s) or phase offset register(s) to the new value. 2. write the nco frequency hold-off counter(s) to the appropriate value (greater than 1 and less than 2^16). 3. write the soft hop synchronization enable bit and the corresponding soft sync channel enable bits high in the soft synchronization configuration register. this starts the countdown by the frequency hold-off counter. when the count reaches 1, the new frequency and/or phase offset is loaded into the nco. hop with pin sync four sync pins (0, 1, 2 and 3) provide very accurate synchro- nization among channels. each channel can be programmed to look at any of the four sync pins. to control the hop of channel nco frequencies: 1. write the nco frequency register(s) or phase offset register(s) to the new value. 2. write the nco frequency hold-off counter(s) to the appropriate value (greater than 1 and less than 2 16 ). 3. program the channel nco control registers to monitor the appropriate sync pins. 4. write the hop synchronization enable bit and sync pin enable bits high in the pin synchronization configuration register. this enables the countdown of the frequency hold-off counter. when the reaches 1, the new frequency and/or phase offset is loaded into the nco. serial port control the AD6636 serial port allows the programming and readback of all control registers and coefficient memory, serially, in 1-byte words. the serial port can work in two modes, selected using the mode pin (spi = 0, sport = 1). in both spi and sport modes, the AD6636 is compatible with blackfin, tigersharc, and other dsps. the serial port and microport share some of the i/o pins; therefore, only one of these ports is operational at a time. the selection between the serial port and microport modes is made using the smode pin (serial port = 1, microport = 0). the serial port has a chip select pin (active low signal), which should be pulled low for any operation on the serial port. serial data can be shifted into the part or out of the part as either msb first or lsb first using the msbfirst pin (1 = msb first, 0 = lsb first). hardware interface the pins listed in table 25 comprise the physical interface between the users programming device and the AD6636 serial port. all serial pins are inputs except for sdo, which is an open- drain output and should be pulled high by an external pull-up resistor (typical value of 1 k?). table 25. serial port pin names and functions pin name function sclk serial clock in both spi and sport modes. serial data is clocked in on the rising edge of sclk. msbfirst indicates whether the first bit sh ifted in or out of the serial port is the msb (1) or lsb (0) of the data word. stfs serial transmit frame sync in sport mode; ignored in spi mode. srfs serial receive frame sync in sport mode; ignored in spi mode. sdi serial data input in both modes. sdo serial data output in both modes. scs active low serial chip select in both modes. setting this pin hi gh holds the serial port in reset. it should be pulled low for any read/write operation on serial port. smode serial mode. partis programmed through the serial port when this pin is logic 1. mode mode pin. selects between spi (0) and sport (1) modes.
AD6636 rev. 0 | page 49 of 72 spi mode w r ite o p er ation i n s p i mo de , t h e sclk r u n s o n l y wh en da ta is bein g tra n s- f e rr ed , so n o e x t e rn al f r a m i n g i s n e c e s s a r y . t h e s p i se ri al m o d e supp or t s sl a v e o p e r a t i o n s on ly . in put d a t a on sdi pi n i s r e g i s t er e d on t h e r i sin g e d g e o f sclk and , t h erefo r e , t h e ds p or mas t er de vice sh o u ld be s e t t o c h a n g e da t a on t h e fal l in g e d ge o f sc l k . all in p u t a n d o u t p u t tra n s f e r s tak e p l a c e i n 8-b i t tra n sa cti o n s . f o r a wr i t e op era t io n, t h e us er m u s t wr i t e tw o 8-b i t ins t r u c t io n w o r d s t o th e s e r i al p o r t t o ins t r u c t th e AD6636 in t e r n al con t r o l log i c a b o u t t h e da t a t o b e wr i t ten. th e f i rs t i n st r u c t io n w o r d is a n addr es s lo c a t i o n . i f t h e m s bfirs t pin is l o g i c 1, t h is addr ess is t h e e n d i n g a ddr ess; i f i t is l o g i c 0, t h is addr ess co r r es p o n d s t o t h e st a r t i n g addr es s. th e s e cond in st r u c t io n w o r d co n t a i n s a 1-b i t r e ad/ w r i te indic a t o r (msb b i t: 1 = r e ad , 0 = wr i t e), fol l o w e d b y a 7- b i t f i e l d t o i n dic a t e t h e n u m b er o f addr es s lo c a t i o n s t o wr i t e (n). f o l l o w in g t h e i n s t r u c t io n w o r d s a r e t h e n wr i t e o p era t ion s (e ach on e b y t e l o n g ), w h er e n i s t h e n u m b er o f addr es s l o c a t i ons to wr i t e. a f te r e a c h w r i t e c y cl e, t h e i n te r n a l addre s s i s i n cr em en t e d (m s b fir s t = 0) o r d e cr e m en t e d (m s b firs t = 1). i n this cas e , ms b f irs t indica t e s the f i rs t b i t co min g ou t o f o r in t o the s p i p o r t as w e l l as whic h b y t e is wr i t t e n f i r s t (m ost sig n if ica n t b y t e o f t h e n-b y t e t r a n sfer). f o r exa m p l e , co n s ider wr i t in g a ddr es s e s 0x01 t o 0x07 o f AD6636 r e g i s t er ma p , w h en o p era t in g in s p i m o de and ms bf irst = 0. the inst r u c t io n w o r d s a r e a ddress e s 0x 01 a nd 0x07 (ms b = 0 f o r wr i t e). th e fol l o w in g s e v e n wr i t e c y cles t r a n sfer o n e b y te a t a t i m e s e q u en t i al ly in t o a d dr es s e s 0x01 t o 0x 07, in t h a t o r der . th e in st r u c t io n w o r d s and d a t a sh o u l d b e wr i t te n w i t h lsb f i rst. i f t h e exa m ple is fo r ms b f irst = 1, t h e n t h e i n s t r u c t io n w o r d s a r e 0x07 (a ddr es s 7) a nd 0x07 (n u m b e r o f addr es s e s t o wr i t e). the da t a co r r es p o n d s t o a d dr es s e s 0x07 t o 0x01, in tha t o r der . the inst r u c t io n w o r d s a nd da t a a r e ms b f i rst. spi mode r e a d o p er ation d a ta o n th e s d o p i n i s s h i f t e d o u t o n th e po s i ti v e e d g e o f sclk. th er efo r e , t h e d s p o r o t h e r mas t er de v i ce sh o u ld r e g i s t er da t a o n t h e fal l i n g e d ge o f sclk. a l l in p u t an d ou t p u t t r a n sfers t a k e pl ace in 8 - b i t t r ans a c t io n s . th e sd o p i n is hig h i m p e da n c e wh en da t a i s n o t bein g o u t p u t . e a ch re ad c y cl e c o ns ists of scs going l o w , eig h t cl o c k c y cl es gen e r a te d o n s c lk p i n, fol l o w e d b y scs pu l l e d h i g h . d a t a co r r es p o n d in g to t h e addr es s e s t o b e r e ad is t r an sfer r e d o u t o n t h e sd o p i n and is r e g i s t er e d b y t h e mas t er de vice on t h e fal l in g e d ge . the da t a is ms b f i rs t o r ls b f i rs t bas e d o n t h e st a t u s of m s bf i r s t p i n . f o r exa m p l e , co n s ider r e adin g a ddr es s e s 0x01 t o 0x07 o f th e AD6636 r e g i s t er ma p , w h en o p era t in g in s p i m o de and ms bf irst = 0. the inst r u c t io n w o r d s a r e a ddress e s 0x 01 a nd 0x87 (ms b = 1 f o r r e ad). th e f o l l o w in g s e v e n r e ad c y c l es t r a n sfer o n e b y te a t a t i m e , s e q u en t i al ly o u t o f a ddr es s e s 0x01 to 0x07, in t h a t o r der . th e in st r u c t io n w o r d s sh o u ld b e wr i t t e n l s b f i r s t , a n d da ta co m e s o u t o n th e s d o wi th th e l s b f i r s t . i f t h e exa m ple is fo r ms b f irst = 1, t h e n t h e i n s t r u c t io n w o r d s a r e 0x07 (a ddr es s 7) a nd 0x87 (ms b = 1 f o r r e a d , f o l l o w ed b y t h e n u m b er o f addr es s lo c a t i o n s t o r e ad). the da t a coming o u t o n s d o co r r es p o n d s t o a ddr ess e s 0x07 t o 0x01, in tha t o r der . the ins t r u c t io n w o r d s a r e wr i t t e n ms b f i rs t, and da t a com e s out on t h e sd o w i t h m s b f i r s t . sclk scs s mode sdi mode t sscs t hsi d0 d1 d2 d3 d4 d5 d6 d7 t ssi t hscs logic 1 logic 0 04998-0-044 f i g u re 44. spi wr it e to t h e a d 6 6 3 6 s e ri al p o r t a n d t r a n s f er of 1- b y te d a t a to i n tern a l r e g i s t ers
AD6636 rev. 0 | page 50 of 72 sclk scs smode sdi sdo mode instruction byte 1 instruction byte 2 valid output 04998-0-045 f i g u re 45. spi r e ad back ti ming spor t mo de w r it e o p er atio n i n s p or t m o d e , t h e sc lk r u ns co n t i n uo usly , a nd ex ter n a l s r fs an d s t fs sig n als a r e us e d fo r f r a m in g o f th e in p u t an d o u t w o r d s. i n comin g f r a m in g sig n als s r fs (r e c ei v e /in p u t ) an d s t fs (tra n s mi t/o u t p u t ) a r e valid w h en t h ey a r e high f o r o n e sclk c y c l e . al l in p u t an d o u t p u t da t a m u s t be t r a n smi t t e d o r r e cei v e d in 8-b i t w o r d s b y usin g t h e a p p r o p r i a t e f r a m in g sig n al s. d u r i n g a wr i t e c y cle , t h e da t a is r e g i s t er e d on t h e r i sin g e d g e of sclk. th er efo r e , t h e p r og ra mmin g de vice o u t p u t s da t a on t h e fal l in g e d g e o f t h e sc lk. the scs p i n is lo w fo r b o t h r e ad and wr i t e c y cles. f o r a wr i t e op era t io n, t h e us er m u s t wr i t e tw o 8-b i t ins t r u c t io n w o r d s t o th e s p o r t t o ins t r u c t th e AD6636 in ter n al co n t r o l log i c a b o u t t h e da t a t o b e wr i t ten. th e f i rs t i n st r u c t io n w o r d is a n addr es s lo c a t i o n . i f ms b f irs t is l o g i c 1, t h is addr es s is t h e endin g a ddr ess; if ms bf irst is l o g i c 0, t h is addr ess is t h e st ar t i ng a d d r e s s . t h e s e c o nd i n s t r u c t i o n word c o n t ai ns a 1 - bi t r e ad/ w r i te i n di c a to r (ms b b i t: 1 = r e ad , 0 = wr i t e), fol l o w e d b y a 7-b i t f i eld to i ndic a te t h e n u m b er o f addr ess l o ca t i on s to wr i t e ( n ) . e a ch wr ite c y cl e t a k e s ni ne cl o c k c y cl es , wit h s r f s hig h on t h e f i rs t clo c k c y cle a n d t h e 8 - b i t ins t r u c t io n wo r d o n t h e n e xt eig h t cl o c k c y cl es . f o l l o w in g t h e i n st r u c t io n w o r d s is n wr i t e o p e r a t io n s (e ach o n e b y t e lo n g ), w h er e n is t h e n u m b er o f addr es s lo ca t i on s t o wr i t e . e a ch wr i t e o p er a t io n m u s t i n clude s r fs hig h fo r o n e clo c k c y cle a n d t h e 8- b i t da t a . af t e r e a ch wr i t e c y cle , t h e i n t e r n al addr ess is i n cr e m e n te d ( m s b f i rs t = 0) o r de c r em e n te d (ms b firs t = 1 ) . i n this cas e , ms b f irs t indica t e s the f i rs t b i t co min g o u t o f o r in t o the s p o r t , as we l l as t h e b y t e tha t is wr i t t e n f i rs t (mos t sig n if ican t b y t e o f t h e n-b y te t r a n sfer , w h e n ms b f irs t = 1) . f o r exa m p l e , co n s ider wr i t in g a ddr es s e s 0x01 t o 0x07 o f AD6636 r e g i s t er ma p , w h en o p era t in g in s p or t m o de an d ms bf irst = 0. the inst r u c t io n w o r d s a r e a ddress e s 0x 01 a nd 0x07 (ms b = 0 f o r wr i t e). the fol l o w in g s e v e n wr i t e c y cles t r a n sfer o n e b y t e a t a t i m e , s e q u en t i al l y in to a ddr es s e s 0x0 1 t o 0x07, in tha t o r der . th e in st r u c t io n w o rds a nd da t a a r e wr i t te n w i t h t h e ls b f i rst. i f t h e exa m ple is fo r ms b f irst = 1, t h e n t h e i n s t r u c t io n w o r d s a r e 0x07 (a ddr es s 7) a nd 0x07 (th e n u m b er o f addr es s e s t o wr i t e). the da t a co r r es p o n d s t o a ddr es s e s 0x07 t h r o ug h t o 0x 01, in t h a t o r der . th e in st r u c t io n w o r d s and d a t a a r e ms b f i rs t. spo r t mo d e r e a d o p er ation d a ta o n th e s d o p i n i s s h i f t e d o u t o n th e po s i ti v e e d g e o f sclk. th er efo r e , t h e d s p o r o t h e r mas t er de v i ce r e g i s t ers da t a on t h e f a l l i n g e d ge of s c l k . a l l i n put a n d output t r ans f e r s t a ke place i n 8- b i t t r a n s a c t io n s . the s d o p i n is hig h im p e dan c e wh e n da ta i s n o t be in g o u t p u t . a r e ad o p er a t ion is simi la r t o a wr i t e op era t io n in i t s fo r m a t . the f i rs t t w o ins t r u c t io n w o r d s a r e wr i t t e n o n t h e s d i p i n, t h e o n ly dif f er en ce b e i n g t h a t t h e ms b b i t o f t h e s e co nd ins t r u c t io n w o r d is t h a t l o g i c 1 indic a t e s a r e ad o p era t io n. af t e r t h e in s t r u c t io n w o rds a r e wr i t t e n, t h e mas t er de vic e ini t i a t e s n r e ad c y cl es . e a ch re ad c y cl e c o ns ists of an s t f s f r aming s i g n a l va l i d fo r o n e clo c k c y cle a nd t h e 8- b i t da t a comin g o u t o n t h e sd o pi n . t h e scs p i n m u s t be lo w d u r i n g th e r e ad c y c l e . da t a co r r es p o n d in g to t h e addr es s e s t o b e r e ad is t r an sfer r e d o u t o n t h e sd o p i n and sh o u ld b e r e g i s t er e d b y t h e mas t er de vice . the da ta is m s b f i r s t o r ls b f i r s t, bas e d o n the s t a t u s o f th e ms b f irs t p i n. f o r exa m p l e , co n s ider r e adin g a ddr es s e s 0x01 t o 0x07 o f AD6636 r e g i s t er ma p , w h en o p era t in g in s p or t m o de an d ms b f irs t = 0. the ins t r u c t io n w o r d s a r e 0x01 a nd 0x87 (ms b = 1 fo r r e ad). th e fol l o w in g s e v e n r e ad c y cles t r a n sfer o n e b y t e a t t i m e , s e q u en tial l y o u t o f a ddr es s e s 0x01 t o 0x07, in tha t o r der . th e i n st r u c t io n w o r d s a r e wr i t te n ls b f i rst a nd t h e d a t a co m e s o u t o n t h e s d o w i t h t h e ls b f i rs t.
AD6636 rev. 0 | page 51 of 72 srfs sclk scs smode sdi d0 d1 d2 d3 d4 d5 d6 d7 mode 04998-0-046 f i gure 46. sport s e ri al write sclk scs smode sdi sdo mode instruction byte 1 instruction byte 2 valid output srfs stfs 04998-0-047 f i gure 47. sport s e ri al r e adb a ck i f t h e exa m ple is fo r ms b f irst = 1, t h e n t h e i n s t r u c t io n w o r d s a r e 0x07 (a ddr es s 7) a nd 0x87 (ms b = 1 f o r r e a d , f o l l o w ed b y t h e n u m b er o f addr es s lo c a t i o n s t o r e ad). the da t a coming o u t o n the s d o co r r es p o n d s t o a d dr es s e s 0x07 t o 0x01, in tha t o r der . th e i n st r u c t io n w o r d s a r e wr i t te n ms b f i rst an d d a t a co m e s o u t o n t h e s d o w i t h t h e ms b f i rs t. c o nne c t in g th e AD6636 s e ri al p o r t to a bla c kfin dsp i n s p i mo de, t h e black f i n ds p m u st ac t a s a master to t h e AD6636 b y p r o v idin g t h e scl k . s d o is an o p en-dra in o u t p u t , s o tha t m u l t i p le s l a v e devices can b e co nn ec ted t o g e th er . f i gur e 48 s h o w s typ i cal in ter c o n n e c t io n s . smode sclk spiss srfs and stfs sck mosi miso scs sdo sdi pf2 mode blackfin (master) AD6636 (slave) programmable flag vddio gnd 04998-0-048 f i gure 48. spi mod e s e ri a l p o r t conn e c t ions to b l ackfin d s p i n s p o r t m o de , t h e blackf in pr o v ides t h e s c l k , s r fs, a nd s t fs sig n als, as s h own in f i gur e 49.
AD6636 rev. 0 | page 52 of 72 smode sclk tfs rfs srfs stfs sck dt dr scs sdo sdi pf2 mode blackfin AD6636 programmable flag vddio gnd 04998-0-049 f i g u re 49. sport m o de s e r i al p o r t con n ec t i ons t o b l a c k f i n dsp microport the micr o p o r t o n the AD6636 ca n be us e d f o r p r og ra mmin g t h e p a r t , r e ading r e g i s t er val u es , a n d r e adin g out p u t da t a (i, q , a nd rss i w o r d s) . n o t e tha t , a t a n y gi v e n po in t in ti m e , e i t h e r th e m i cr o p o r t o r th e se ri al po r t ca n b e a c ti v e , b u t n o t bo th . s o m e o f th e balls o n th e p a cka g e a r e s h ar e d b e tw e e n t h e micr o p o r t a nd t h e s e r i al p o r t a nd ha ve d u a l f u n c t i o n a l i t y b a s e d o n t h e s m ode p i n. t h e m i c r op or t i s s e l e c t e d by pu l l i n g t h e smode pi n l o w ( g rou n d ) . b o t h r e ad and wr i t e op er a t io ns ca n b e p e r f o r m e d usin g t h e micr o p o r t. the dir e c t ad dr essing s c h e me is us e d an d a n y in t e r n al r e g i st er ca n be acces s e d usin g a n 8-b i t addr es s. th e da t a b u s can b e ei t h er 8-b i t o r 1 6 -b i t as s e t b y t h e chi p i/o acces s co n t r o l r e g i s t er . m i cr o p or t o p era t io n is s y n c hr on o u s t o cpucl k , which m u s t be s u p p l i ed ext e r n al t o t h e AD6636 p a r t . cpucl k sh o u l d b e les s than clk a an d 100 m h z. the micr o p o r t ca n op era t e i n i n t e l mo de (s ep ara t e r e ad an d w r ite st ro b e s ) o r i n m o toro l a m o d e ( s i n g l e re a d / w r i te st ro b e ) . the m o d e p i n is us ed t o s e lec t betw een i n t e l ( i nm, m o d e = 0) a nd m o t o r o l a (mnm, m o d e = 1) m o des. s o m e AD6636 pi ns h a ve d u a l f u nc t i on a l i t y b a s e d on t h e mod e pi n . t a bl e 2 6 li s t s th e p i n fu n c ti o n s f o r bo th m o d e s . table 26. microport programming pins pin name intel mode motorola mod e reset reset reset smode logic 0 logic 0 mode logic 0 logic 1 a [ 7 : 0 ] a [ 7 : 0 ] a [ 7 : 0 ] d [ 1 5 : 0 ] d [ 1 5 : 0 ] d [ 1 5 : 0 ] r/ w ( wr ) wr r/ w ds ( rd ) rd ds dtack (rdy) rdy dtack cs cs cs int e l (inm) mo d e the p r og ra mmin g p o r t p e r f o r m s sy n c hr on o u s i n te l-sty l e r e ads a nd wr i t es on t h e p o si t i v e e d g e o f t h e cp ucl k in p u t w h en res e t is inac t i v e (ac t iv e lo w sig n a l ). the cp ucl k pin is dr i v en b y the p r og ra mmin g de vice (cpuclk o f ds p o r fpga). d u r i n g a wr i t e acce s s , t h e a[7:0] addr e s s b u s p r o v ides t h e addr es s fo r acces s , an d t h e d[15:0] b u s (d[7:0] if t h e 8- b i t da t a b u s is us e d ) is dr i v en b y t h e p r og ra mmin g de vice . the da t a b u s is dr i v en b y th e AD6636 d u r i n g a r e ad o p er a t io n. i n te l m o de us es s e p a ra t e r e ad ( rd ) a nd wr i t e ( wr ) a c ti v e - l o w d a ta st r o b e s to i ndic a te b o t h t h e ty p e o f access an d t h e va li d d a t a fo r tha t acces s . the chi p s e le c t ( cs ) is a n ac t i v e -low in pu t t h a t sig n a l s w h e n an acces s is ac ti ve o n i t s p r og ra mmin g p o r t p i n s . dur i n g a n access, th e AD6636 dr iv es rd y lo w t o indic a te tha t i t is p e r f o r min g the acces s . w h en the in ter n al r e ad o r wr i t e ac ces s is co m p let e , t h e rd y pin p u l l e d hig h . b e c a us e t h e r d y p i n is an o p e n -drain o u t p u t wi th a w e ak in t e rn al p u l l - u p r e si s t o r (70 k ? ), a n ext e rn al pu l l - u p re s i stor i s re c o m m e nd e d ( s e e f i g u re 5 0 ) . f i g u re 1 3 and f i gur e 14 a r e t h e t i mi n g dia g ram s fo r r e ad a n d wr i t e c y cles u s i n g t h e m i c r op or t i n i n m m o d e . f o r a n asy n chr o n o us wr i t e o p era t io n in i n te l (i nm) mo de , t h e cpucl k sh o u l d b e r u nning. s e t u p t h e d a t a and addr ess b u s e s. pu l l t h e wr sig n al l o w a nd th en p u l l th e cs sig n al lo w . th e rd y g o es lo w to in dic a t e tha t t h e ac ces s is tak i n g p l ace in t e r n al ly . w h e n rd y g o es hi g h , t h e wr i t e c y cle is co m p lete and cs ca n be p u l l e d hig h t o dis a b l e t h e micr o p o r t. f o r an a s y n ch ro nou s re a d op e r at i o n on t h e i n tel mo d e micr o p o r t, s e t up t h e addr es s b u s a n d t h r e e-st a t e t h e da t a b u s. pu l l t h e rd sig n al l o w a nd th en p u l l th e cs sig n al lo w . th e rd y g o es lo w to in dic a t e an in ter n al acces s . w h en rd y g o es lo w , valid da t a is a v a i la b l e on t h e da t a b u s f o r r e ad . mot o r o la (mnm) mod e the p r o g r a mmi n g p o r t p e r f o r m s sy n c hr on o u s m o to r o la-sty le r e ads a nd wr i t es o n the p o si ti ve edg e o f cpuclk w h en res e t is inac t i v e (ac t i v e lo w sig n al). th e a[7:0] b u s p r o v ides t h e addr es s t o acce ss a nd t h e d[15: 0] b u s (d[7:0], i f t h e 8-b i t da t a b u s is us e d ) is e x ter n a l ly dr i v en wi t h da t a d u r i ng a wr i t e ( d r i ve n b y th e AD6636 d u r i n g a r e ad). m o t o r o la m o de us es th e r/ w lin e t o in dica t e t h e typ e o f access (log ic 1 = r e ad , log i c 0 = wr i t e), and t h e ac t i v e -lo w da t a st r o b e ( ds ) sig n al i s us ed t o indic a te va lid d a t a .
AD6636 rev. 0 | page 53 of 72 the chip select ( cs ) is an active-low input that signals when an access is active on its programming port pins. when the read/write cycle is complete, the AD6636 drives dtack low. the dtack signal goes high again after either the cs or ds signal is driven high. because the dtack pin is an open-drain output with a weak internal pull-up resistor (70 k?), an external pull-up resistor is recommended (see figure 50). figure 15 and figure 16 are the timing diagrams for read and write cycles using the microport in mnm mode. for an asynchronous write operation on the motorola mode microport, the cpuclk should be running. set up the data and address buses. pull the r/ w and ds signals low and then pull the cs signal low. the dtack goes low after a few clock cycles to indicate that the write access is complete and that cs can be pulled high to disable the microport. for an asynchronous read operation on the motorola mode microport, set up the address bus and three-state the data bus. pull the rd signal low and then pull the cs signal low. the dtack goes low after a few clock cycles to indicate that valid data is on the data bus. accessing multiple AD6636 devices if multiple AD6636 devices are on a single board, the microport pins for these devices can be shared. in this configuration, a single programming device (dsp, fpga, or microcontroller) can program all AD6636 devices connected to it. each AD6636 has four chipid pins that can be connected in 16 different ways. during a write/read access, the internal circuitry checks to see if the chipid bits in the chip i/o access control register (address 0x02) are the same as the logic levels of the chipid pins (hardwired to the part). if the chipid bits and the chipid pins have the same value, then a write/read access is completed; otherwise, the access is ignored. to program multiple devices using the same microport control and data buses, the devices should have separate chipid pin configurations. a write/read access can be made only on the intended chip; all other chips would ignore the access. jtag boundary scan the AD6636 supports a subset of the ieee standard 1149.1 specification. for details of the standard, see the ieee standard test access port and boundary-scan architecture , an ieee-1149 publication. the AD6636 has five pins associated with the jtag interface. these pins, listed in table 27, are used to access the on-chip test access port. all input jtag pins are pull-up except for tclk, which is pull-down. table 27. boundary scan test pins name description trst test access port reset tclk test clock tms test access port mode select tdi test data input tdo test data output the AD6636 supports three op codes, listed in table 28. these instructions set the mode of the jtag interface. table 28. boundary scan op codes instruction op code bypass 11 sample/preload 01 extest 00 a bsdl file for this device is available. contact analog devices inc. for more information. extest (2'b00) places the ic into an external boundary-test mode and selects the boundary-scan register to be connected between tdi and tdo. during this operation, the boundary-scan register is accessed to drive-test data off-chip via boundary outputs and receive test data off-chip from boundary inputs. sample/preload (2'b01) allows the ic to remain in normal functional mode and selects the boundary-scan register to be connected between tdi and tdo. the boundary-scan register can be accessed by a scan operation to take a sample of the functional data entering and leaving the ic. also, test data can be preloaded into the boundary scan register before an extest instruction. bypass (2'b11) allows the ic to remain in normal functional mode and selects a 1-bit bypass register between tdi and tdo. during this instruction, serial data is transferred from tdi to tdo without affecting operation of the ic.
AD6636 rev. 0 | page 54 of 72 memory map reading the memory map table each row in the memory map table has four address locations. the memory map is roughly divided into four regions: global register map (addresses 0x00 to 0x0b), input port register map (addresses 0x0c to 0x67), cha nnel register map (addresses 0x68 to 0xbb), and output port register map (addresses 0xbc to 0xe7). the channel register map is shared by all six channels, and access to individual channels is given by the channel i/o access control register (address 0x02). in the memory map, table 29, the addresses are given in the right column. the column with the heading byte 0 has the address given in the right column. the column byte 1 has the address given by 1 more than the address listed in the right column (address offset of 1). similarly, the address offset for the byte 2 column is 2, and for the byte 3 column is 3. for example, the second row lists 0x04 as the address in the right column. the pin synchronization configuration register has address 0x04, the soft synchronization configuration register has address 0x05, and the lvds cont rol register lists addresses 0x07 and 0x06. bit format all registers are in little-endian format. for example, if a register takes 24 bits or three address locations, then the most significant byte is at the highest address location and the least significant byte is at a lowest address location. in all registers, the least significant bit is bit 0 and the most significant bit is bit 7. for example, the nco frequency <31:0> register is 32 bits wide. bit 0 (lsb) of this register is written at bit 0 of address 0x70 and bit 32 (msb) of this register is written at bit 7 of address 0x73. when referring to a register that takes up multiple address locations, it is referred to by the address location of the most significant byte of the register. for example, the text reads, port a dwell timer at address 0x2a. note that only the four most significant bits of this register are at this location, and this register also takes up addresses 0x29 and 0x28. open locations all locations marked as open are currently not used. when required, these locations should be written with 0s. writing to these locations is required only when part of an address location is open (for example, address 0x78). if the whole address location is open (for example, address 0x00), then this address location does not need to be written. if the open locations are readback using the microport or serial port, the readback value is undefined (each bit can be independently 1 or 0), and these bits have no significance. if an address location has more than one register or has one register with some open bits, then the order of these registers is as given in the table. for example, address 0x33 reads open <7:5>, port a signal monitor <4:0>. the open <7:5> is located at bits <7:5> and the port a signal monitor <4:0> is located at bits <4:0>. another example is address 0x35: open <15:10>, port a upper threshold <9:0> here, bits <7:2> of address 0x35 are open <15:10>. bits <1:0> of address 0x35 and bits <7:0> of address 0x34 make up the port a upper threshold <9:0> register (bit 1 of address 0x35 is the msb of the port a upper threshold register). default values on coming out of reset, some of the address locations (but not all) are loaded with default values. when available, the default values for the registers are given in the table. if the default value is not listed, then these address locations are in an undefined state (logic 0 or logic 1) on reset . logic levels in the explanation of various registers, bit is set is synonymous with bit is set to logic 1 or writing logic 1 for the bit. similarly clear a bit is synonymous with bit is set to logic 0 or writing logic 0 for the bit.
AD6636 rev. 0 | page 55 of 72 table 29. memory map 8-bit hex address byte 3 byte 2 byte 1 byte 0 8-bit hex address 0x03 open <7:6>, channel enable <5:0> open<7:6>, channel i/o access control<5:0> chip i/o access control <7:0> (default 0x00) open<7:0> 0x00 0x07 open <15:11>, lvds cont rol<10:0> (default 0x06fc) soft synchronization configuration<7:0> pin synchronization configuration<7:0> 0x04 0x0b interrupt mask <15:0> interrupt sta tus <15:0> (read only , default 0x00) 0x08 adc input port register mapaddresses 0x0c to 0x67 0x0f adc input control <31:0> 0x0c 0x13 open<15:0> adc clk contro l <15:0> (default 0x0000) 0x10 0x17 port ab, iq correction control<15: 0> (default 0x0000) port cd, iq correct ion control <15:0> (default 0x0000) 0x14 0x1b port ab, dc offset correction i<15:0> port ab, dc offset correction q<15:0> 0x18 0x1f port cd, dc offset correction i<15:0> port cd, dc offset correction q<15:0> 0x1b 0x23 port ab, phase offset corre ction <15:0> port ab, amplitud e offset correction <15:0> 0x20 0x27 port cd, phase offset corre ction <15:0> port cd, amplitud e offset correction <15:0> 0x24 0x2b port a gain control <7:0> open<23: 20>, port a dwell timer <19:0> 0x28 0x2f open<7:0> port a power monitor period <23:0> 0x2c 0x33 open<7:5>, port a signal monitor<4:0> port a power monito r output <23:0> 0x30 0x37 open<15:10>, port a lower threshold <9:0> open <15:10>, port a upper threshold <9:0> 0x34 0x3b port b gain control <7:0> open<23: 20>, port b dwell timer <19:0> 0x38 0x3f open<7:0> port b power monitor period <23:0> 0x3c 0x43 open<7:5>, port b signal monitor<4:0> port b power monito r output <23:0> 0x40 0x47 open<15:10>, port b lower threshold <9:0> open <15:10>, port b upper threshold <9:0> 0x44 0x4b port c gain control <7:0> open<23: 20>, port c dwell timer <19:0> 0x48 0x4f open<7:0> port c power monitor period <23:0> 0x4c 0x53 open<7:5>, port c signal monitor<4:0> port c power monitor output <23:0> 0x50 0x57 open<15:10>, port c lower threshold <9:0> open <15:10>, port c upper threshold <9:0> 0x54 0x5b port d gain control <7:0> open<23: 20>, port d dwell timer <19:0> 0x58 0x5f open<7:0> port d power monitor period <23:0> 0x5c 0x63 open<7:5>, port d signal monitor<4:0> port d power monitor output <23:0> 0x60 0x67 open<15:10>, port d lower threshold <9:0> open <15:10>, port d upper threshold <9:0> 0x64 channel register mapaddresses 0x68 to 0xbb 0x6b open<15:0> open<15:9>, nco control<8:0> 0x68 0x6f nco start hold-off counter<15:0> nc o frequency hold-off counter<15:0> 0x6c 0x73 nco frequency <31:0> (default 0x0000 0000) 0x70 0x77 open<15:0> nco phase offs et<15:0> (default 0x0000) 0x74 0x7b open<7:1>, cic bypass<0> open<7:5>, cic decimation<4:0> open<7:5>, cic scale factor<4:0> open<7:4>, fir-hb control<3:0> 0x78 0x7f open<15:0> open<15:13>, mrcf control<12:0> 0x7c 0x83 open<7:6>, mrcf coefficient 3 <5:0> open<7:6>, mrcf coefficient 2 <5:0> open<7:6>, mrcf coefficient 1 <5:0> open<7:6>, mrcf coefficient 0 <5:0> 0x80 0x87 open<7:6>, mrcf coefficient 7 <5:0> open<7:6>, mrcf coefficient 6 <5:0> open<7:6>, mrcf coefficient 5 <5:0> open<7:6>, mrcf coefficient 4 <5:0> 0x84 0x8b open<15:13>, drcf control register<12:0> open <7:6>, drcf coefficient offset<5:0> open<7>, drcf taps <6:0> 0x88 0x8f open<15:0> open <7:6>, drcf final address<5:0> open <7:6>, drcf start address<5:0> 0x8c 0x93 open<15:0> open<15:14>, drcf coefficient memory <13:0> 0x90
AD6636 rev. 0 | page 56 of 72 8-bit hex address byte 3 byte 2 byte 1 byte 0 8-bit hex address 0x97 open<15:13>, crcf control register<12:0> open <7:6>, crcf coefficient offset<5:0> open<7>, crcf taps <6:0> 0x94 0x9b open<15:0> open <7:6>, crcf final address<5:0> open <7:6>, crcf start address<5:0> 0x98 0x9f open<7:0> open<23:20>, crcf coefficient memory <19:0> 0x9c 0xa3 open<15:11>, agc control register< 10:0> agc hold-off register<15:0> 0xa0 0xa7 open<15:12>, agc update decimation<11:0> open<15:12>, agc signal gain <11:0> 0xa4 0xab open<15:12>, agc error threshold <11:0> open<7:6>, agc average samples<5:0> agc pole location <7:0> 0xa8 0xaf open<7:0> agc desired level<7:0> agc loop gain2 <7:0> agc loop gain1 <7:0> 0xac 0xb3 open<7:0> bist i path signature regist er<23:0> (read-only, default 0xAD6636) 0xb0 0xb7 open<7:0> bist q path signature regist er<23:0> (read-only, default 0xAD6636) 0xb4 0xbb open <15:0> bist control <15:0> 0xb8 output port register mapaddresses 0xbc to 0xe7 0xbf open<7:0> parallel port output control <23:0> 0xbc 0xc3 open<15:0> open<15:10>, output port control <9:0> 0xc0 0xc7 agc0, i output<15:0> (read only) ag c0, q output <15:0> (read only) 0xc4 0xcb agc1, i output <15:0> (read only) agc1, q output <15:0> (read only) 0xc8 0xcf agc2, i output <15:0> (read only) agc2, q output <15: 0> (read only) 0xcc 0xd3 agc3, i output <15:0> (read only) agc3, q output <15:0> (read only) 0xd0 0xd7 agc4, i output <15:0> (read only) agc4, q output <15:0> (read only) 0xd4 0xdb agc5, i output <15:0> (read only) agc5, q output <15:0> (read only) 0xd8 0xdf open<15:12>, agc0 rssi output< 11:0> (read only) open<15:12>, agc1 r ssi output<11:0> (read only) 0xdc 0xe3 open<15:12>, agc2 rssi output< 11:0> (read only) open<15:12>, agc3 r ssi output<11:0> (read only) 0xe0 0xe7 open<15:12>, agc4 rssi output< 11:0> (read only) open<15:12>, agc5 r ssi output<11:0> (read only) 0xe4 global register map chip i/o access control register <7:0> <7>: synchronous microport bit. when this bit is set, the microport assumes that its controls signals (such as r/ w , ds , and cs ,) are synchronous to the cpuclk. when cleared, asynchronous control signals are assumed, and the microport control signals are resynchronized with cpuclk inside the AD6636 part. synchronous microport (when bit is set) has the advantage of requiring a fewer number of clock cycles for read/write access. <6>: this bit is open. <5:2>: chip id bits. the chip id bits are used to compare against the chip id input pins, enabling or disabling i/o access for this specific chip. when more than one AD6636 part is sharing the microport, different chipid pins can be used to differentiate among the parts. a particular part gives i/o access only when the chipid pins have the same value as these chip id bits. <1>: this bit is open. <0>: byte mode bit. the byte mode bit selects the bit width for the microport operation. table 30 shows details. table 30. microport data bus width selection chip access control register <0> microport data bus bit width 0 (default) 8-bit mode, using d<7:0> 1 16-bit mode, using d<15:0> channel i/o access control register <5:0> these bits enable/disable the channel i/o access capability. <5>: channel 5 access bit. when the channel 5 access bit is set to logic 1, any i/o write operation (from either the microport or the serial port) that addresses a register located within the channel register map updates the channel 5 registers. similarly, for a read operation, the contents of the desired address in the channel register map are output when this bit is set to logic 1.
AD6636 rev. 0 | page 57 of 72 <4>: channel 4 access bit. similar to bit <5> for channel 4. <3>: channel 3 access bit. similar to bit <5> for channel 3. <2>: channel 2 access bit. similar to bit <5> for channel 2. <1>: channel 1 access bit. similar to bit <5> for channel 1. <0>: channel 0 access bit. similar to bit <5> for channel 0. note: if the access bits are set for more than one channel, during write access all channels with access are written with same the data. this is especially useful when more than one channel has similar configurations. during a read operation, if more than one channel has access, the read access is given to the channel with the lowest channel number. for example, if both channel 4 and channel 2 have access bits set, then read access is given to channel 2. channel enable register <5:0> <5>: channel 5 enable bit. when this bit is set, channel 5 logic is enabled. when this bit is cleared, channel 5 is disabled and the channels logic does not consume any power. on power-up, this bit comes up with logic 0 and the channel is disabled. a start sync does not start channel 5 unless this bit is set before issuing the start sync. <4>: channel 4 enable bit. similar to bit <5> for channel 4. <3>: channel 3 enable bit. similar to bit <5> for channel 3. <2>: channel 2 enable bit. similar to bit <5> for channel 2. <1>: channel 1 enable bit. similar to bit <5> for channel 1. <0>: channel 0 enable bit. similar to bit <5> for channel 0. pin synchronization configuration <7:0> <7>: hop synchronization enable bit. this bit is a global enable for any hop synchronization involving sync pins. when this bit is set, hop synchronization is enabled for all channels that are programmed for pin synchronization. when this bit is cleared, hop synchronization is not performed for any channel that is programmed for pin synchronization. <6>: start synchronization enable bit. this bit is a global enable for any start synchronization involving sync pins. when this bit is set, start synchronization is enabled for all channels that are programmed for pin synchronization. when this bit is cleared, start synchronization is not performed for any channel that is programmed for pin synchronization. <5>: first sync only bit. when this bit is set, the nco synchronization logic recognizes only the first synchronization event as valid. all other requests for synchronization events are ignored as long as this bit is set. when cleared, all synchro- nization events are acted upon. <4>: edge-sensitivity bit. when this bit is set, the rising edge on the sync pin(s) is detected as a synchronization event (edge- sensitive detection). when cleared, logic 1 on the sync pin(s) is detected as a synchronization event (level-sensitive detection). <3>: enable synchronization from sync3 bit. when this bit is set, the sync3 pin can be used for synchronization. when this bit is cleared, the sync3 pin is ignored. this is a global enable for all sync pins, and each individual channel selects which pin it listens to. <2>: enable synchronization from sync2 bit. similar to bit <3> for the sync[2] pin. <1>: enable synchronization from sync1 bit. similar to bit <3> for the sync1 pin. <0>: enable synchronization from sync0 bit. similar to bit <3> for the sync0 pin. soft synchronization configuration <7:0> <7>: soft hop synchronization enable bit. when this bit is set, hop synchronization is enabled for all channels selected using bits 5:0. when this bit is cleared, hop synchronization is not performed for any channels selected using bits 5:0. <6>: soft start synchronization enable bit. when this bit is set, start synchronization is enabled for all channels selected using bits 5:0. when this bit is cleared, start synchronization is not performed for any channels selected using bits 5:0. bits<5:0> form the soft_sync control bits. these bits can be written to by the controller to initiate the synchronization of a selected channel. <5>: soft sync channel 5 enable bit. when this bit is set, it enables channel 5 to receive a hop sync or start sync, as defined by bits 7 and 6, respectively. when cleared, channel 5 does not receive any soft sync. <4>: soft sync channel 4 enable bit. similar to bit <5> for channel 4. <3>: soft sync channel 3 enable bit. similar to bit <5> for channel 3. <2>: soft sync channel 2 enable bit. similar to bit <5> for channel 2. <1>: soft sync channel 1 enable bit. similar to bit <5> for channel 1. <0>: soft sync channel 0 enable bit. similar to bit <5> for channel 0.
AD6636 rev. 0 | page 58 of 72 lvds control register <10:0> <10>: cmos mode bit. when this bit is set, the adc ports operate in cmos mode. when this bit is cleared, the adc ports operate in lvds mode. the default is logic 1 or cmos mode. in lvds mode, two cmos adc port pins are used to form one differential pair of lvds adc ports. <9>: reserved. this bit should always be written logic 1. <8>: autocalibrate enable bit. when this bit is set, the auto- calibration cycle is invoked for the lvds pads. at the end of calibration, this calibration value is set for the lvds pads. when this bit is cleared, the output for the lvds controller is taken from manual calibration value (bits <7:0> of this register). <7:4>: these bits are open. <3:0>: manual calibration value bits. the value of these bits is used for manual lvds calibration. when the autocalibrate bit is set, these bits are dont care. interrupt status register <15:0> this register is read-only. <15>: agc 5 rssi update interrupt bit. if the agc 5 update interrupt enable bit is set, this bit is set by the AD6636 whenever agc 5 updates a new rssi word (the new word should be different from the previous word). if the agc 5 update interrupt enable bit is cleared, then this bit is not set (not updated). an interrupt is not generated in this case. note: for bits <15:10>, no interrupt is generated, if the new rssi word is the same as the previous rssi word. <14>: agc 4 rssi update interrupt bit. similar to bit <15> for the agc 4. <13>: agc 3 rssi update interrupt bit. similar to bit <15> for the agc 3. <12>: agc 2 rssi update interrupt bit. similar to bit <15> for the agc 2. <11>: agc 1 rssi update interrupt bit. similar to bit <15> for the agc 1. <10>: agc 0 rssi update interrupt bit. similar to bit <15> for the agc 0. <9>: channel 5 data ready interrupt bit. this bit is set to logic 1 whenever the channel bist signature registers are loaded with data. the conditions required for setting this bit are: the channel bist signature registers is programmed for bist signature generation and the channel 5 data ready enable bit in the interrupt enable register is cleared. if the channel 5 data ready enable bit in the interrupt enable register is set, the AD6636 does not set this bit on signature generation and an interrupt is not generated. <8>: channel 4 data ready interrupt bit. similar to bit <9> for channel 4. <7>: channel 3 data ready interrupt bit. similar to bit <9> for channel 3. <6>: channel 2 data ready interrupt bit. similar to bit <9> for channel 2. <5>: channel 1 data ready interrupt bit. similar to bit <9> for channel 1. <4>: channel 0 data ready interrupt bit. similar to bit <9> for channel 0. <3>: adc port d power monitoring interrupt bit. this bit is set by the AD6636 whenever the adc port d power monitor interrupt enable bit is set and the port d power monitor timer runs out (end of the port d power monitor period). if the adc port d power monitoring interrupt enable bit is cleared, the AD6636 does not set this bit and does not generate an interrupt. note: in real input cmos mode, all four input ports exist. in complex input cmos mode, only adc ports a and c function. in real input lvds mode, only adc ports a and c function. <2>: adc port c power monitoring interrupt bit. similar to bit <3> for adc port c. <1>: adc port b power monitoring interrupt bit. similar to bit <3> for adc port b. <0>: adc port a power monitoring interrupt bit. similar to bit <3> for adc port a. interrupt enable register <15:0> <15>: agc 5 rssi update enable bit. when this bit is set, the agc 5 rssi update interrupt is enabled, allowing an interrupt to be generated when the rssi word is updated. when this bit is cleared, an interrupt cannot be generated for this event. also, see the interrupt status register <15:0> section. <14>: agc 4 rssi update enable bit. similar to bit <15> for the agc 4. <13>: agc 3 rssi update enable bit. similar to bit <15> for the agc 3. <12>: agc 2 rssi update enable bit. similar to bit <15> for the agc 2. <11>: agc 1 rssi update enable bit. similar to bit <15> for the agc 1. <10>: agc 0 rssi update enable bit. similar to bit <15> for the agc 0.
AD6636 rev. 0 | page 59 of 72 <9>: channel 5 data ready enable bit. when this bit is set, the channel 5 data ready interrupt is enabled, allowing an interrupt to be generated when channel 5 bist signature registers are updated. when this bit is cleared, an interrupt cannot be generated for this event. <8>: channel 4 data ready enable bit. similar to bit <9> for channel 4. <7>: channel 3 data ready enable bit. similar to bit <9> for channel 3. <6>: channel 2 data ready enable bit. similar to bit <9> for channel 2. <5>: channel 1 data ready enable bit. similar to bit <9> for channel 1. <4>: channel 0 data ready enable bit. similar to bit <9> for channel 0. <3>: adc port d power monitoring enable bit. when this bit is set to logic 1, the adc port d power monitoring interrupt is enabled allowing an interrupt to be generated when adc port d power monitoring registers are updated. when set to logic 1, the adc port d power monitoring interrupt is disabled. <2>: adc port c power monitoring enable bit. similar to bit <3> for adc port c. <1>: adc port b power monitoring enable bit. similar to bit <3> for adc port b. <0>: adc port a power monitoring enable bit. similar to bit <3> for adc port a. input port register map adc input control register <27:0> these bits are general control bits for the adc input logic. <27>: pn active bit. when this bit is set, the pseudorandom number generator is active. when this bit is cleared, the pn generator is disabled and the seed is set to its default value. <26>: exp lock bit. when this bit is set along with the pn active bit, then the exp signal for pseudorandom input is locked to 000 (giving full-scale input). when this bit is cleared, exp bits for pseudorandom input are randomly generated input data bits. <25>: port c complex data active bit. when this bit is set, the data inputs on ports c and d are interpreted as complex inputs (port c for the in-phase signal and port d for the quadrature phase signal). this complex input is passed on as the input from adc port c. when this bit is cleared, the data on adc port c and adc port d interpreted as real and independent input. note that complex input mode is available only in cmos input mode. <24>: port a complex data active bit. when this bit is set, the data input on ports a and b is interpreted as complex input (port a for the in-phase signal and port b for the quadrature phase signal). this complex input is passed on as input from adc port a. when this bit is cleared, the data on adc port a and adc port b is interpreted as real and independent input. note that complex input mode is available only in cmos input mode. <23>: channel 5 complex data input bit. when this bit is set, channel 5 gets complex input data from the source that is selected by the crossbar mux select bits. when this bit is cleared, channel 5 receives real input data. (see table 31.) <22:20>: channel 5 crossbar mux select bits. these bits select the source of input data for channel 5. (see table 31.) table 31. channel 5 input configuration complex data input bit crossbar mux select bits configuration 0 000 adc port a drives input (real). 0 001 adc port b drives input (real). 0 010 adc port c drives input (real). 0 011 adc port d drives input (real). 0 100 pn sequence drives input (real). 1 000 ports a and b drive complex input. 1 001 ports c and d drive complex input. 1 010 pn sequence drives complex input. <19>: channel 4 complex data input bit. similar to bit <23> for channel 4. <18:16>: channel 4 crossbar mux select bits. similar to bits <22:20> for channel 4. <15>: channel 3 complex data input bit. similar to bit <23> for channel 3. <14:12>: channel 3 crossbar mux select bits. similar to bits <22:20> for channel 3. <11>: channel 2 complex data input bit. similar to bit <23> for channel 2. <10:8>: channel 2 crossbar mux select bits. similar to bits <22:20> for channel 2.
AD6636 rev. 0 | page 60 of 72 <7>: channel 1 complex data input bit. similar to bit <23> for channel 1. <6:4>: channel 1 crossbar mux select bits. similar to bits <22:20> for channel 1. <3>: channel 0 complex data input bit. similar to bit <23> for channel 0. <2:0>: channel 0 crossbar mux select bits. similar to bits <22:20> for channel 0. adc clk control register <11:0> these bits control the adc clocks and internal pll clock. <11>: adc port d clk invert bit. when this bit is set, the inverted adc port d clock is used to register adc input port d data into the part. when this bit is cleared, the clock is used as is, without any inversion or phase change. <10>: adc port c clk invert bit. similar to bit <11> for adc port c. <9>: adc port b clk invert bit. similar to bit <11> for adc port b. <8>: adc port a clk invert bit. similar to bit <11> for adc port a. <7:6>: adc pre pll clock divider bits. these bits control the pll clock divider. the pll clock is derived from the adc port a clock. table 32. pll clock divider select bits pll clock divider bits 12:11 divide-by value 00 divide-by-1, bypass 01 divide-by-2 10 divide-by-4 11 divide-by-8 <5:1>: pll clock multiplier bits. these bits control the pll clock multiplier. the output of the pll clock divider is multiplied with the binary value of these bits. the valid range for the multiplier is from 4 to 20. a value outside this range powers down the pll, and the pll clock is the same as the adc port a clock. <0>: this bit is open (write logic 0). port ab, i/q correction control <15:0> <15:12>: amplitude loop bw. these bits set the decimation value used in the integrator for the amplitude offset-estimation feedback loop. a value of 0 sets a decimation of 2 12 and a value of 11 sets decimation of 2 24 . each increment of these bits increases the decimation value by a power of 2. <11:8>: phase loop bw. these bits set the decimation value used in the integrator for the phase offset-estimation feedback loop. a value of 0 sets a decimation of 2 12 and a value of 11 sets decimation of 2 24 . each increment of these bits increases the decimation value by a power of 2. <7:4>: dc loop bw. these bits set the decimation and interpolation value used in the low-pass filters for the dc offset estimation feedback loop. a value of 0 sets a decimation/ interpolation of 2 12 and a value of 11 sets decimation/ interpolation of 2 24 . each increment of these bits increases the decimation/interpolation value by a power of 2. <3>: reserved. <2>: port ab amplitude correction enable bit. when the amplitude correction enable bit is set, the amplitude correction function of the i/q correction logic for the ab port is enabled. when this bit cleared, the amplitude correction value is given by the value of the ab amplitude correction register. if the port a complex data active bit of the adc input control register is cleared (real input mode), this bit is a dont care. <1>: port ab phase correction enable bit. when this bit is set, the phase correction function of the i/q correction logic for the ab port is enabled. when this bit is cleared, the phase correc- tion value is given by the value of the ab phase correction register. if the port a complex data active bit of the adc input control register is cleared (real input mode), this bit is a dont care. <0>: port ab dc correction enable bit. when this bit is set, the dc offset correction function of the i/q correction block for the ab port is enabled. when this bit is cleared, the dc offset correction value is given by the value of the ab offset correction registers. if the port a complex data active bit of the adc input control register is cleared (real input mode), this bit is a dont care. port cd, i/q correction control <15:0> <15:12>: amplitude loop bw. these bits set the decimation value used in the integrator for the amplitude offset estimation feedback loop. a value of 0 sets a decimation of 2 12 and a value of 11 sets decimation of 2 24 . each increment of these bits increases the decimation value by a power of 2. <11:8>: phase loop bw. these bits set the decimation value used in the integrator for the phase offset estimation feedback loop. a value of 0 sets a decimation of 2 12 and a value of 11 sets decimation of 2 24 . each increment of these bits increases the decimation value by a power of 2. <7:4>: dc loop bw. these bits set the decimation and interpolation value used in the low pass filters for the dc offset estimation feedback loop. a value of 0 sets a decimation/ interpolation of 2 12 and a value of 11 sets decimation/ interpolation of 2 24 . each increment of these bits increases the decimation/interpolation value by a power of 2. <3>: reserved.
AD6636 rev. 0 | page 61 of 72 <2>: port cd amplitude correction enable bit. when this bit is set, the amplitude correction function of the i/q correction logic for the ab port is enabled. when this bit is cleared, the amplitude correction value is given by the value of the ab amplitude correction register. if the port a complex data active bit of the adc input control register is cleared (real input mode), this bit is a dont care. <1>: port cd phase correction enable bit. when this bit is set, the phase correction function of the i/q correction logic for the ab port is enabled. when this bit is cleared, the phase correction value is given by the value of the ab phase correction register. if the port a complex data active bit of the adc input control register is cleared (real input mode), this bit is a dont care. <0>: port cd dc correction enable bit. when the dc correction enable bit is set, the dc offset correction function of the i/q correction block for the ab port is enabled. when cleared, the dc offset correction value is given by the value of the ab offset correction registers. if the port a complex data active bit of the adc input control register is cleared (real input mode), this bit is a dont care. port ab, dc offset correction i <15:0> this register holds the in-phase signal dc offset correction value for complex data stream when dc correction is enabled. this value should be set manually when automatic correction is disabled. this 16-bit value is subtracted from the 16-bit adc port a data (in-phase signal). this data is a dont care in real input mode. port ab, dc offset correction q <15:0> this register holds the quadrature phase signal dc offset correction value for complex data stream when dc correction enabled. this value should be set manually when automatic correction is disabled. this 16-bit value is subtracted from the 16-bit adc port b data (quadrature phase signal). this data is a dont care in real input mode. port cd, dc offset correction i <15:0> this register holds the in-phase signal dc offset correction value for complex data stream when dc correction is enabled. this value should be set manually when automatic correction is disabled. this 16-bit value is subtracted from the 16-bit adc port c data (in-phase signal). this data is a dont care in real input mode. port cd, dc offset correction q <15:0> this register holds the quadrature phase signal dc offset correction value for complex data stream when dc correction is enabled. this value should be set manually when automatic correction is disabled. this 16-bit value is subtracted from the 16-bit adc port d data (quadrature phase signal). this data is a dont care in real input mode. port ab, phase offset correction <15:0> this register holds the phase offset correction value for complex data stream when the ab port phase correction is enabled. this value is set manually when automatic correction is disabled. this value is calculated as tan(phase_mismatch), where phase_mismatch is the mismatch in phase between i (in-phase signal) and q (quadrature phase signal). this 14-bit value is multiplied with 16-bit q (quadrature phase signal, input port b) and added to 16-bit i (in-phase signal, input port a). this data is a dont care in real input mode. port ab, amplitude offset correction <15:0> this register holds the amplitude offset correction value for complex data stream when the ab port amplitude correction is enabled. this value is set manually when automatic correction is disabled. this value is calculated as (mag(q) ? mag(i)), where i is the in-phase signal and q is the quadrature phase signal. this 14-bit value is multiplied with 16-bit q (quadrature phase signal, input port b) and added to 16-bit q (quadrature phase signal, input port b). this data is a dont care in real input mode. port cd, phase offset correction <15:0> this register holds the phase offset correction value for the complex data stream when cd port phase correction is enabled. this value should be set manually when automatic correction is disabled. this value should be calculated as tangent (phase_mismatch), where phase_mismatch is the mismatch in phase between i (in-phase signal) and q (quadrature phase signal). this 14-bit value is multiplied with 16-bit q (quadrature phase signal, input port d) and added to 16-bit i (in-phase signal, input port c). this data is a dont care in real input mode. port cd, amplitude offset correction <15:0> this register holds the amplitude offset correction value for complex data stream when cd port amplitude correction is enabled. this value is set manually when automatic correction is disabled. this value is calculated as (mag(q) ? mag(i)), where i is the in-phase signal and q is the quadrature phase signal. this 14-bit value are multiplied with 16-bit q (quadrature phase signal, input port d) and added to 16-bit q (quadrature phase signal, input port d). this data is a dont care in real input mode. port a gain control <7:0> <7>: this bit is open. <6:1>: this 6-bit word specifies the relinearization pipe delay to be used in the adc input gain control block. the decimal representation of these bits is the number of input clock cycle pipeline delays between the external exp data output and the internal application of relinearization based on exp.
AD6636 rev. 0 | page 62 of 72 <0>: gain control enable bit. this bit controls the configura- tion of the exp<2:0> bits for channel a. when the gain control enable bit is logic 1, the exp<2:0> bits are configured as outputs. when this bit is cleared, the exp<2:0> bits are inputs. port a dwell timer <19:0> this register is used to set the dwell time for the gain control block. when gain control block is active and detects a decrease in the signal level below the lower threshold value (program- mable), a dwell time counter is initiated to provide temporal hysteresis. doing so prevents the gain from being switched continuously. note that the dwell timer is turned on only after a drop below the lower threshold is detected in the signal level. port a power monitor period <23:0> this register is used in the power monitoring logic to set the period of time for which adc input data is monitored. this value represents the monitor period in number of adc port clock cycles. port a power monitor output <23:0> this register is read-only and contains the current status of the power monitoring logic output. the output is dependent on the power monitoring mode selected. when the power monitor block is enabled, this register is updated at the end of each power monitor period. this register is updated even if an interrupt signal is not generated. port a upper threshold <9:0> this register serves the dual purpose of specifying the upper threshold value in the gain control block and in the power monitoring block, depending on which block is active. any adc port input data having a magnitude greater than this value triggers a gain change in the gain control block. any adc port input data having a magnitude greater than this value is monitored in the power monitoring block (in peak detect or threshold crossing mode). the value of the register is compared with the absolute magnitude of the input port data. for real input, the absolute magnitude is the same as the input data; for positive and negative data, the absolute magnitude is the value of the data after removing the negative sign. port a lower threshold <9:0> this register is used in the gain control block and represents the magnitude of the lower threshold for adc port input data. any adc input data having a magnitude below the lower threshold initiates the dwell time counter. the value of the register is compared with the absolute magnitude of the input port data. for real input, the absolute magnitude is the same as the input data; for positive and negative data, the absolute magnitude is the value of the data after removing the negative sign. port a signal monitor <4:0> this register controls the functions of the power monitoring block. <4>: disable power monitor period timer bit. when this bit is set, the power monitor period timer no longer controls the update of the power monitor holding register. a user read to the power monitor holding register updates this register. when this bit is cleared, the power monitor period register controls the timer and, therefore, controls the update rate of the power monitor holding register. <3>: clear-on-read bit. when this bit is set, the power monitor holding register is cleared every time this register is read. this bit controls whether the power monitoring function is cleared after a read of the power monitor period register. if this bit is set, the monitoring function is cleared after the read. if this bit is logic 0, the monitoring function is not cleared. this bit is a dont care if the disable integration counter bit is clear. <2:1>: monitor function select bits. table 33 lists the functions of these bits. table 33. monitor function select bits monitor function select function enabled 00 peak detect mode 01 mean power monitor mode 10 threshold crossing mode 11 invalid selection <0>: monitor enable bit. when this bit is set, the power monitoring function is enabled and operates as selected by bits <2:1> of the signal monitor register. when this bit is cleared, the power monitoring function is disabled and the signal monitor register <2:1> bits are dont care. this bit defaults to 0 on power-up. note: gain control, dwell timer, power monitor period, signal monitor, power monitoring output, lower threshold and upper threshold registers for ports b, c, and d work similarly to the corresponding registers definitions for port a. channel register map channel control registers are common to all six channels, and access to specific channels is determined by the channel i/o access register (address 0x02). nco control <15:0> these bits control the nco operation. <8:7>: nco sync start select bits. these bits determine which sync input pin is used by this channel for a start synchroniza- tion operation. table 34 describes the selection. table 34. sync start select bits nco control 8:7 sync pin sed for start synchroniation 00 sync0 01 sync1 10 sync2 11 sync3
AD6636 rev. 0 | page 63 of 72 <6:5>: nc o s y n c h o p s e le c t bi ts. th es e b i ts det e r m i n e w h ich s y nc in p u t p i n is us e d b y t h is cha n n e l fo r a h o p syn c hr o n iz a - t i o n o p er a t io n. t a b l e 35 des c r i b e s t h e s e le c t io n. ta ble 35. s y nc hop select bi t s nco control < 6 :5> sync pin used f o r hop synchronization 0 0 s y n c 0 0 1 s y n c 1 1 0 s y n c 2 1 1 s y n c 3 <4>: this b i t is o p en. <3>: n c o b y p a s s b i t. w h en this b i t is s e t, t h e n c o is b y p a ss e d s h u t s d o wn f o r po w e r sa vin gs. t h is b i t ca n b e used f o r po w e r sa vi n g s , w h en n c o f r eq ue n c y o f d c o r 0 h z i s r e q u i r ed . w h en t h is b i t is cle a r e d , t h e n c o o p e r a t es as p r og ra mme d . <2>: c l e a r n c o a c c u m u la t o r b i t. w h en t h is b i t is s e t, t h e cle a r n c o acc u m u l a t o r b i t sy n c hr ono u s l y cle a rs t h e phas e acc u m u - la t o r on a l l f r e q uen c y h o ps i n t h is cha n n e l. w h en t h is b i t is cl e a re d, t h e ac c u m u l a tor is not cl e a re d and ph a s e c o n t in u o u s h o ps a r e im p l em en t e d . <1>: p h as e di t h er ena b le b i t. w h en this b i t is s e t, p h as e di t h er in g i n t h e n c o is enab le d. w h e n t h is b i t i s cle a r e d , phas e di t h er in g is dis a b l e d . <0>: am pl i t ude di t h er ena b le bi t. w h en t h is b i t is s e t, a m pli t ude di t h e r in g in t h e nc o is ena b le d . w h e n t h is b i t is cl e a re d, am pl i t u d e di t h er ing is dis a bl e d . cha nnel s t a r t hol d - o ff co un ter <1 5: 0> w h e n a st ar t s y nch r on i z a t i o n ( s of t w are or h a r d w a re ) o c c u r s o n th e c h ann e l , t h e val u e in this r e g i s t er is lo aded in t o a do wn- co un t e r . w h en t h e co u n t e r has f i nish e d co un ting do wn t o 0, t h e ch an nel op e r a t i o n i s st ar te d. nc o f r e q uenc y hop h o ld- o ff c o unte r < 1 5: 0> w h en a h o p sy n c o c c u rs, a co u n ter is lo ade d w i t h t h e n c o fr e q u e n c y h o l d - o ff r e g i s t e r v a l u e . t h e 1 6 - b i t c o u n t e r s t a r t s c o u n t i ng d o w n . w h e n i t re a c he s 0 , t h e ne w f r e q u e nc y v a lu e i n t h e s h ado w r e g i s t er is wr i t t e n t o t h e n c o f r e q u e n c y r e g i s t er . (s ee the n u m e r i call y c o n t r o lled o s cilla t o r (n co) sectio n . ) nc o f r e q uenc y <3 1:0> the val u e i n t h i s r e g i s t er is us e d t o p r og ra m t h e n c o t u nin g f r e q uen c y . th e val u e t o b e p r og ra mme d is g i ve n b y t h e f o l l ow i n g e q u a t i on : n c o f r eq u e nc y re g i s t er = clk frequency nco _ 2 32 w h er e: n c o_freq uency is t h e desir e d nc o t u ning f r e q uen c y . clk is t h e ad c clo c k ra te . the val u e g i v e n b y t h e e q ua t i on s h o u ld b e lo ade d i n t o t h e re g i ste r i n bi n a r y f o r m a t . nc o phase o f f s et <15: 0> the val u e i n t h e r e g i s t er is lo ade d in t o t h e phas e acc u m u l a t o r o f t h e n c o b l o c k e v er y t i m e a s t ar t syn c o r h o p s y n c is r e ce i v e d b y t h e cha n nel. this a l lo ws indivi d u a l chan n e ls to b e st a r te d wi t h a k n own no nzer o phas e . th e n c o phas e o f fs et is n o t lo ade d o n a h o p syn c , if b i t <2> o f t h e nc o co n t r o l r e g i s t er (cle a r phas e acc u m u la t o r o n h o p) is cle a r e d . this n c o o f fs et r e g i st er va l u e is in t e r p r e t e d as a 16-b i t un sig n e d in teger . a 0x0000 in this r e g i s t er co r r es p o n d s t o a 0 radian o f fs et, a nd a 0xffff co r r es po n d s t o an o f fset o f 2 (1 ? 1/(2 16 )) rad i a n s. cic bypass <0> w h en t h is b i t is s e t, t h e en t i r e c i c f i l t er is b y p a s s e d . the output of c i c f i lte r i s d r ive n s t r a i g h t f r om t h e i n put w i t h out a n y cha n ge . w h en t h is b i t is cle a r e d , t h e ci c f i lt er o p era t es in n o rm al m o d e as p r ogra m m e d . w r i t in g logi c 1 t o th i s b i t dis a b l es b o t h t h e ci c de c i m a t i o n o p er a t io n and t h e ci c s c a l in g op era t ion. cic d e ci mation <4: 0 > this 5- b i t w o r d sp e c if ies t h e cic f i l t er de cima t i o n va l u e min u s 1. a val u e o f 0x00 is a decima tio n o f 1 (b yp as s), a n d 0x1f is a d e c i m a t i on of 3 2 . w r it i n g a v a lu e of 0 i n t h i s re g i ste r by p a ss e s ci c f i l t er ing, b u t do es n o t b y p a ss t h e cic s c a l in g o p er a t io n. cic s c ale f a c t or < 4 : 0 > this 5- b i t w o r d sp e c if ies t h e cic f i l t er s c a l e fac t o r us e d t o co m p e n s a t e fo r t h e ga i n p r o v ide d b y t h e ci c f i l t er . the r e co mme n d e d val u e is g i v e n b y t h e fol l o w in g e q u a t i o n : cic s c a l e reg i ster = ce il (5 log 2 ( m cic )) ? 5 w h er e: m cic is t h e de ci ma t i on ra te o f t h e c i c (on e m o r e t h a n t h e val u e in t h e cic de ci ma t i on r e g i st er) . ce il op era t ion g i v e s t h e clos es t i n t e g e r g r e a t e r t h a n o r e q u a l t o th e a r g u m e n t . the vali d ra n g e fo r t h is r e g i s t er is de cimal 0 t o 20. fir-hb c o nt rol <3: 0 > <3>: fir1 ena b le b i t. w h en t h is b i t is s e t, t h e f i r1 f i x e d- co ef f i cien t f i l t er is ena b le d . w h e n cle a r e d , fir1 is b y p a s s e d . <2>: hb1 enab le b i t. w h e n t h is b i t is s e t, t h e h b 1 half-b an d f i l t er is ena b le d . w h en cle a r e d , hb1 is b y p a s s e d . <1>: fir2 ena b le b i t. w h en t h is b i t is s e t, t h e f i r2 f i x e d- co ef f i cien t f i l t er is ena b le d . w h e n cle a r e d , fir2 is b y p a s s e d . <0>: hb2 enab le b i t. w h e n t h is b i t is s e t, t h e h b 2 half-b an d f i l t er is ena b le d . w h en cle a r e d , hb2 is b y p a s s e d .
AD6636 rev. 0 | page 64 of 72 mrcf control register <12:0> <12:10>: mrcf data select bits. these bits are used to select the input source for the mrcf filter. each mrcf filter can be driven by output from the hb2 filter of any channel independ- ently. table 36 shows the selections available. table 36. mrcf data select bits mrcf data select2:0 mrcf input source 000 mrcf input taken from channel 0 001 mrcf input taken from channel 1 010 mrcf input taken from channel 2 011 mrcf input taken from channel 3 1x0 mrcf input taken from channel 4 1x1 mrcf input taken from channel 5 <9>: interpolating half-band enable bit. when this bit is set, the interpolating half-band filter, driven by the output of the crcf block, is enabled. when cleared, the interpolating half- band filter is bypassed and its output is the same as its input. the interpolating half-band filter doubles the data rate. <8>: this bit is open. <7>: half-rate bit. when this bit is set, the mrcf filter operates using half the pll clock rate. this is used for power savings when there is sufficient time to complete mrcf filtering using only half the pll clock rate. when this bit is cleared, the mrcf filter operates at the full pll clock rate. (see the mono-rate ram coefficient filter section.) <6:4>: mrcf number of taps bits. this 3-bit word should be written with one less than the number of taps that are calculated by the mrcf filter. the filter length is given by the decimal value of this register plus 1. a value of 0 represents a 1-tap filter and maximum value of 7 represents an 8-tap filter. <3:2>: mrcf scale factor bits. the output of the mrcf filter is scaled according to the value of these bits. table 37 describes the attenuation corresponding to each setting. table 37. mrcf scale factor mrcf scale1:0 scale factor 00 18.06 db attenuation (left-shift 3 bits) 01 12.04 db attenuation (left-shift 2 bits) 10 6.02 db attenuation (left-shift 1 bit) 11 no scaling (0 db) <1>: this bit is open. <0>: mrcf bypass bit. when this bit is set, the mrcf filter is bypassed and, therefore, the output of the mrcf is the same as its input. when this bit is cleared, the mrcf has normal operation as programmed by its control register. mrcf coefficient memory the mrcf coefficient memory consists of eight coefficients, each six bits wide. the memory extends from address 0x80 to address 0x87. the coefficients should be written in twos complement format. drcf control register <11:0> <11>: drcf bypass bit. when this bit is set, the drcf filter is bypassed and, therefore, its output is the same as its input. when this bit is cleared, the drcf has normal operation as pro- grammed by the rest of this control register. <10>: symmetry bit. when this bit is set, it indicates that the drcf is implementing a symmetrical filter and only half the impulse response needs to be written into the drcf coefficient ram. when this bit is cleared, the filter is asymmetrical and complete impulse response of the filter should be written to the coefficient ram. when this filter is symmetrical, it can implement up to 128 filter taps. <9:8>: drcf multiply accumulate scale bits.the output of the drcf filter is scaled according to the value of these bits. table 38 lists the attenuation corresponding to each setting. table 38. drcf multiply accumulate scale bits drcf scale1:0 scale factor 00 18.06 db attenuation (left-shift 3 bits) 01 12.04 db attenuation (left-shift 2 bits) 10 6.02 db attenuation (left-shift 1 bit) 11 no scaling (0 db) <7:4>: drcf decimation rate. this 4-bit word should be written with one less than the decimation rate of the drcf filter. a value of 0 represents a decimation rate of 1 (no rate change), and the maximum value of 15 represents a decimation of 16. filtering can be implemented irrespective of the decimation rate. <3:0>: drcf decimation phase bits. this 4-bit word represents the decimation phase used by the drcf filter. the valid range is 0 up to m drcf ? 1, where m drcf is the decimation rate of the drcf filter. this word is primarily used for synchronization of multiple channels of the AD6636, when more than one channel is used for filtering one signal (one carrier). drcf coefficient offset <7:0> this register is used to specify which section of the 64-word coefficient memory is used for a filter. it can be used to select between multiple filters that are loaded into memory and referenced by this pointer. this register is shadowed, and the filter pointer is updated every time a new filter is started. this allows the coefficient offset to be written even while a filter is being computed without disturbing operation. the next sample comes out of the drcf with the new filter.
AD6636 rev. 0 | page 65 of 72 drcf taps <6:0> this register is written with one less than the number of taps that are calculated by the drcf filter. the filter length is given by the decimal value of this register plus 1. a value of 0 represents a 1-tap filter, and a value of 0x28 (40 decimal) represents a 41-tap filter. drcf start address <5:0> this register is written with the starting address of the drcf coefficient memory to be updated. drcf final address <5:0> this register is written with the ending address of the drcf coefficient memory to be updated. drcf coefficient memory <13:0> drcf memory. this memory consists of 64 words, and each word is 14 bits wide. the data written to this memory space is expected to be 14-bit, twos complement format. see the decimating ram coefficient filter section for the method to program the coefficients into the coefficient memory. crcf control register <11:0> <11>: crcf bypass bit. when this bit is set, the drcf filter is bypassed and, therefore, its output is the same as its input. when this bit is cleared, the crcf has normal operation as pro- grammed by its control register. <10>: symmetry bit. when this bit is set, it indicates that the crcf is implementing a symmetrical filter and only half the impulse response needs to be written into the crcf coefficient ram. when this bit is cleared, the filter is asymmetrical and the complete impulse response of the filter should be written into the coefficient ram. when this filter is symmetrical, it can implement up to 128 filter taps. <9:8>: crcf multiply accumulate scale bits. the output of the crcf filter is scaled according to the value of these bits. table 39 lists the attenuation corresponding to each setting. table 39. crcf multiply accumulate scale bits crcf scale1:0 scale factor 00 18.06 db attenuation (left-shift 3 bits) 01 12.04 db attenuation (left-shift 2 bits) 10 6.02 db attenuation (left-shift 1 bit) 11 no scaling (0 db) <7:4>: crcf decimation rate. this 4-bit word should be written with one less than the decimation rate of the crcf filter. a value of 0 represents a decimation rate of 1 (no rate change) and the maximum value of 15 represents a decimation of 16. filtering operation is done irrespective of the decimation rate. <3:0>: crcf decimation phase. this 4-bit word represents the decimation phase used by the crcf filter. the valid range is 0 to m crcf ? 1, where m crcf is the decimation rate of the crcf filter. this word is primarily used for synchronization of multiple channels of the AD6636, when more than one channel is used for filtering one signal (one carrier). crcf coefficient offset <5:0> this register is used to specify which section of the 64-word coefficient memory is used for a filter. it can be used to select between multiple filters that are loaded into memory and referenced by this pointer. this register is shadowed, and the filter pointer is updated every time a new filter is started. this allows the coefficient offset to be written even while a filter is being computed without disturbing operation. the next sample comes out of the crcf with the new filter. crcf taps <6:0> this register is written with one less than the number of taps that are calculated by the crcf filter. the filter length is given by the decimal value of this register plus 1. a value of 0 represents a 1-tap filter, and a value of 0x28 (40 decimal) represents a 41-tap filter. crcf coefficient memory crcf memory. this memory has 64 words that have 20 bits each. the memory contains the crcf filter coefficients. the data written to this memory space is 20-bit in twos complement format. see the channel ram coefficient filter section for the method to program the coefficients into the coefficient memory. agc control register <10:0> <10>: channel sync select bit. when this bit is set, the agc uses the sync signal from the channel for its synchronization. when this bit is cleared, the sync pin used for synchronization is defined by bits <9:8> of this register. <9:8>: sync pin select bits. when bit <10> of this register is cleared, these bits specify the sync pin used by agc for synchronization. these bits are dont care when bit <10> of the agc control register is set to logic 1. table 40. sync pin select bits agc control bits 9:8 sync pin sed by agc 00 sync0 01 sync1 10 sync2 11 sync3
AD6636 rev. 0 | page 66 of 72 <7:5>: a g c w o r d l e n g t h c o n t r o l b i ts. th es e b i ts def i n e t h e w o r d len g th o f th e a g c o u t p u t . the o u t p u t w o r d can be 4 t o 8, 10, 12, o r 16 b i ts wide . t a b l e 41 sh o w s the p o s s ible s e lec t io n s . table 41. agc word le ngth control bits agc control bi ts <7:5 > output word l e ngth (bits) 0 0 0 1 6 0 0 1 1 2 0 1 0 1 0 0 1 1 8 1 0 0 7 1 0 1 6 1 1 0 5 1 1 1 4 <4>: a g c m o de b i t. w h e n t h is b i t is s e t, t h e a g c o p era t es t o ma in t a i n a desire d sig n a l le ve l. w h en t h is b i t is cle a r e d , i t o p era t es t o ma i n t a i n a con s t a n t cli p p i ng le v e l. s e e t h e a u t o m a ti c g a in c o n t r o l secti o n f o r d e ta ils a b o u t th e s e m o d e s . <3>: a g c s y n c n o w bi t. this b i t is us e d t o sy n c hr o n iz e a pa r t i c ula r a g c i r r e s p ecti v e o f th e c h a n n e l th r o u g h th e p r o g r a m m i n g po rt s ( m i c r o p o rt o r s e r i a l p o rt ) . w h e n t h i s b i t i s se t , th e a g c b l oc k u p da t e s a n e w o u t p u t sa m p l e (r s s i sa m p l e ) a nd st a r ts w o rk i n g to wa r d a ne w u p d a te s a m p l e . <2>: i n i t ialize o n s y n c b i t. this b i t is us ed t o det e r m ine w h et h e r o r n o t t h e a g c sh o u ld ini t ia l i ze o n a sy n c . w h e n t h is b i t is s e t, d u r i n g a sy n c hr o n iz a t ion t h e c i c f i l t er is cle a r e d and ne w va l u es fo r ci c de cima t i o n , n u m b er o f a v era g i n g s a m p les, cic s c ale , sig n al ga in gs ga in k, and p o le p a ram e t e r p a r e lo ade d . w h en b i t <2> = 0, t h e ab o v e- men t ion e d p a ramet e rs a r e n o t u p da te d , and t h e ci c f i l t er is no t cle a r e d . i n b o t h cas e s a n a g c u p da te s a m p le is o u t p u t f r o m th e ci c f i l t er and the decima t o r s t a r ts o p era t in g t o wa r d s t h e n e x t o u t p ut s a m p le w h e n e v er a syn c o c c u rs. <1>: f i rst s y n c on ly . this b i t is us e d t o ig n o r e r e p e t i t i ve syn c hr o n iza t ion sig n als. i n s o me a p p l ica t ion s , t h e s y n c hr o n iza - tio n sig n al o c c u r s p e r i o d ical l y . i f this b i t is c l ea r e d , eac h syn c hr o n i z a t ion r e q u est r e syn c hr o n ize s t h e a g c. i f t h is b i t is s e t, o n ly t h e f i rs t o c c u r r en ce c a us es t h e a g c t o syn c hr o n i z e a nd u p da t e s t h e a g c ga in val u es p e r i o d ical l y , dep e n d in g on t h e d e c i m a t i on f a c t or of t h e a g c c i c f i lte r . <0>: a g c b y p a s s b i t. w h e n t h i s b i t is s e t, t h e a g c s e c t ion is b y p a s s e d . the n- b i t r e p r es en t a t i o n f r o m t h e i n t e r p ol a t in g half- b a nd f i l t ers is s t i l l r e d u ce d t o a l o w e r b i t wi d t h rep r es en t a t i on as se t b y b i t s < 7 : 5 > o f th e a g c co n t r o l r e gi s t e r . a tr u n ca ti o n a t th e o u t p u t o f th e a g c a cco m p li s h e s th i s ta s k . a g c hol d - o ff r egister <15: 0> the a g c h o ld- o f f co un t e r is loade d w i t h t h e v a l u e wr i t t e n t o t h is addr es s w h en ei t h er a s o f t syn c o r p i n sy nc co m e s i n t o t h e c h a n n e l . the coun t e r beg i ns coun tin g do wn. w h en i t r e ach e s 1, a s y n c i s sen t t o th e a g c . t h i s syn c mi gh t o r m i gh t n o t ini t iali ze t h e a g c, as def i n e d b y t h e co n t r o l w o r d . the a g c lo o p is u p da ted wi t h a new s a m p le f r o m th e ci c f i l t er w h enever a sy n c o c c u rs. i f t h is r e g i st er is l o g i c 1, t h e a g c is u p da t e d imm e di a t e l y w h en t h e sy n c o c c u rs. i f t h is r e g i s t er l o g i c 0, t h e ag c c a n n o t b e s y n c h r o n i z e d . a g c up da te d e cima tion < 1 1: 0> this 12-b i t r e g i s t er s e ts t h e a g c decima tion ra tio f r o m 1 t o 4096. an a p p r op r i a t e s c al in g fac t o r s h o u ld be s e t t o a v o i d los s o f b i t s . th e d e ci ma ti o n ra ti o i s gi v e n b y th e d e ci mal v a l u e o f th e a g c u p da t e de cima tio n <11:0 > r e g i s t er co n t en ts p l us 1, tha t is, 120x000 descr i bes a decima tio n ra tio o f 1, a n d 120xfff des c r i bes a decima tion ra tio o f 4096. a g c s i gna l g a i n <1 1: 0> this r e g i st er is us e d t o s e t t h e i n i t ia l va l u e fo r a sig n a l ga in us e d in t h e ga i n m u l t i p lier . this 12- b i t val u e s e ts t h e ini t ial sig n al ga in in the ra n g e o f 0 db an d 96 .296 db in s t eps o f 0.024 db . i n i t ial sig n al gain (sg) in db sho u ld be co n v er ted t o a r e g i s t er s e t t in g usin g t h e fol l o w in g fo rm u l a: re gis t er v a l u e = roun d ? ? ? ? ? ? 256 ) 2 ( log 20 10 sg a g c e r r o r th re shold <1 1: 0> this 12- b i t r e g i s t er is t h e co m p a r is o n val u e us e d t o det e r m i n e w h ich lo o p gain va l u e (k 1 or k 2 ) t o us e fo r o p t i m u m op era t ion. w h en t h e ma g n i t ude-o f -er r o r sig n al is les s t h a n t h e a g c er r o r th r e s h o l d v a l u e , th en k 1 is us e d ; o t h e r w is e , k 2 is us e d . th e w o r d fo r m a t o f t h e a g c er r o r t h r e s h old r e g i s t er is fo ur b i ts t o t h e lef t o f th e b i n a r y po i n t a n d e i g h t b i ts t o th e ri gh t . s e e th e a u t o ma ti c ga in c o n t r o l s e c t io n fo r det a i l s . re gis t er v a l u e = roun d ? ? ? ? ? ? 256 ) 2 ( log 20 10 threshold error a g c a v er age s a mples <5: 0 > this 6- b i t r e g i s t er co n t a i n s t h e s c ale us e d fo r t h e ci c f i l t er and t h e n u m b er o f p o w e r s a m p les to b e a v era g e d b e fo r e b e in g s e n t t o t h e c i c f i l t er . <5:2>: ci c s c al e . this 4- b i t w o r d def i n e s t h e s c ale us e d fo r t h e c i c f i l t e r . e a c h i n cr em en t o f thi s w o r d in cr ea ses th e ci c s c ale b y 6.02 db . <1:0>: n u m b er o f a g c a v era g e sa m p les. this def i n e s t h e n u m b er o f s a m p les t o b e a v erag e d b e fo r e t h e y a r e s e n t t o t h e ci c de c i ma t i n g f i l t er . s e e t a b l e 42. table 42. nu m b er o f agc a v erage samples agc aver age s a mples <1: 0 > number of sa mples taken 0 0 1 0 1 2 1 0 3 1 1 4
AD6636 rev. 0 | page 67 of 72 ag c p o l e l o c a t i o n < 7 : 0 > this 8-b i t r e g i s t er is us ed t o def i ne the o p en-lo o p f i l t er p o le lo ca tion p . i t s va l u e ca n be s e t f r o m 0 t o 0.996 in s t eps o f 0.003 9. this val u e o f p is u p da t e d in t h e a g c lo o p eac h time the a g c is ini t ia li ze d . th is o p en-lo o p p o le lo ca t i on dir e c t ly im p a c t s t h e c l osed - l oo p po le loca ti o n s , a s exp l a i n e d i n t h e a u t o m a ti c g a in co n t r o l s e c t i o n . a g c d e sire d le v e l <7: 0 > this r e g i ster con t a i n s t h e desire d sig n a l le vel or desir e d cli p pi n g le vel, de p e n d i n g o n o p er a t io na l m o d e . this des i r e d r e q u est le vel (r) ca n be s e t in db f r o m 0 t o 23.99 in s t eps o f 0.094 db . th e r e q u es t le v e l (r ) in db sh o u l d b e co n v er t e d t o a r e g i s t er s e t t in g usin g t h e fol l o w in g fo r m u l a: re gis t er v a l u e = roun d ? ? ? ? ? ? 64 ) 2 ( log 20 10 r ag c l o o p g a i n 2 < 7 : 0 > this 8- b i t r e g i ster is us e d to def i ne t h e s e cond p o ssi b le op en - lo o p ga in, k 2 . i t s val u e can b e s e t f r o m 0 t o 0.996 in s t eps o f 0.0039. this val u e o f k 2 is u p da t e d each time the a g c is ini t ia li ze d . w h e n t h e ma g n i t ud e-o f -er r o r sig n a l in t h e lo o p is gr ea t e r th a n t h e a g c e r r o r th r e s h o l d , t h en k 2 is us ed b y th e lo o p . k 2 is u p da t e d on ly w h en t h e a g c is in i t ia lize d . ag c l o o p g a i n 1 < 7 : 0 > this 8-b i t r e g i s t er is us ed t o def i ne the o p en-lo o p ga in k 1 . i t s val u e can b e s e t f r o m 0 t o 0.996 in s t eps o f 0.0039. this val u e o f k is u p d a t e d i n t h e a g c lo o p e a ch t i m e t h e a g c is in i t ia l i ze d. w h en t h e ma g n i t ude-o f -er r o r sig n al in t h e lo o p is les s t h a n t h e a g c e r ror t h resho l d, t h e n k 1 is us ed b y th e lo o p . k 1 is u p da te d o n ly w h en t h e a g c is ini t ia l i z e d . i p a th signature r e gist e r < 1 5: 0> this 16- b i t sig n a t ur e r e g i st er is fo r t h e i p a t h o f t h e chann e l l o gi c . t h e s i gn a t u r e r e gi s t e r r e co r d s d a ta o n th e n e t w o r k s tha t lea v e t h e c h a n ne l log i c, j u s t bef o r e en t e r i n g t h e s e co nd da ta route r . q p a th signat ure r egister <15:0> this 16- b i t sig n a t ur e r e g i st er is fo r t h e q p a t h of t h e cha n ne l l o gi c . t h e s i gn a t u r e r e gi s t e r r e co r d s d a ta o n th e n e t w o r k s tha t lea v e t h e c h a n ne l log i c, j u s t bef o r e en t e r i n g t h e s e co nd da ta route r . bis t contr o l < 23: 0> <15>: dis a b l e si g n a t ur e g e n e ra t i o n b i t. w h en t h is b i t is ac t i ve hig h , t h e sig n a t ur e r e g i s t ers do n o t p r o d uce a ps eudo ra ndo m o u t p u t val u e , b u t in s t e a d dir e c t ly lo ad t h e 24- b i t in p u t da t a . w h en t h is b i t is cle a r e d , t h e sig n a t ur e r e g i s t er p r o d uces a ps eudo ra n d om o u t p ut fo r e v er y clo c k c y cle t h a t i t is ac t i ve . s e e t h e u s er -c o n f i g u ra b l e b u i l t-i n s e lf- t est (b ist) s e c t io n fo r det a i l s. <14:0>: b i s t t i m e r b i ts. th e <14:0> b i ts o f this r e g i s t er f o r m a 15-b i t w o r d t h a t is lo ade d in t o t h e bist t i m e r . af t e r lo adin g t h e b i st t i m e r , t h e sig n a t ur e r e g i s t er is ena b le d fo r o p era t ion w h i l e th e tim e r i s a c ti v e l y co u n ti n g do w n . (s ee t h e u s e r - c o n f i g u ra b l e b u i l t-i n s e lf- t e s t (b ist) s e c t ion.) output port register map t h i s pa rt o f t h e m e m o r y m a p d e a l s w i th th e o u t p u t d a ta a n d c o n t r o l s f o r pa r a ll e l o u t p u t po r t s . p a r a llel p o r t output c o ntrol <31:0> <23>: p o r t c a p p e nd rs s i b i t. w h en t h is b i t is s e t, a n r s s i w o r d i s a p pen d ed t o ev e r y i/ q o u t p u t sa m p le , i r r e s p ecti v e o f w h et her t h e rs s i w o r d is u p da t e d i n t h e a g c. w h en t h is b i t is c l ea r e d , a n rs s i w o r d is a p p e n d ed t o an i/q o u t p u t s a m p le o n l y when t h e rss i w o r d is u p da t e d. th e rss i w o r d is n o t o u t p u t f o r s u b s eq u e n t i/ q s a m p l e s u n ti l t h e n e x t t i m e th e r s s i i s u p d a t e d in t h e a g c. <22>: p o r t c, d a ta f o r m a t bi t. w h en this b i t is s e t, th e p o r t is c o n f i g u r ed f o r 8 - b i t pa rall e l i / q m o de . w h e n c l ea r e d , th e po r t i s co nf igur ed f o r 16-b i t in t e rle a v e d i/q m o de . s ee th e p a ral l e l p o r t o u t p u t s e c t ion fo r det a i l s. <21>: p o r t c, a g c 5 ena b le b i t. w h en this b i t is s e t, a g c 5 da t a (i/q da ta) is o u t p u t o n pa ralle l ou t p u t p o r t c (da t a b u s). w h en this b i t is c l ea r e d , a g c 5 da ta do es n o t a p p e a r o n ou t p u t po r t c . <20>: p o r t c, a g c 4 ena b le b i t . simi la r t o b i t <21> fo r a g c 4 . <19>: p o r t c, a g c 3 ena b le b i t . simi la r t o b i t <21> fo r a g c 3 . <18>: p o r t c, a g c 2 ena b le b i t . simi la r t o b i t <21> fo r a g c 2 . <17>: p o r t c, a g c 1 ena b le b i t . simi la r t o b i t <21> fo r a g c 1 . <16>: p o r t c, a g c 0 ena b le b i t . simi la r t o b i t <21> fo r a g c 0 . <15>: p o r t b a p p e nd rs s i b i t. w h en t h is b i t is s e t, a n r s s i w o r d i s a p pen d ed t o ev e r y i/ q o u t p u t sa m p le , i r r e s p ecti v e o f w h et her o r n o t t h e rs s i w o r d i s u p da t e d in t h e a g c. w h en t h i s b i t is c l ea r e d , an rss i w o r d is a p p e nde d t o a n i / q o u t p u t s a m p l e o n l y when t h e rss i w o r d is u p da t e d . th e rs s i w o r d is n o t o u t p u t f o r s u b s e q u e n t i/ q s a m p le s u n til th e n e xt tim e t h e r s s i is u p d a te d in t h e a g c. <14>: p o r t b , da ta f o r m a t bi t. w h en this b i t is s e t, th e p o r t is co nf igur e d fo r 8-b i t p a ra l l e l i/q m o d e . w h en t h is b i t is cle a r e d , t h e p o r t is co nf i g ur e d fo r 16-b i t in t e rle a v e d i/q m o de . s e e t h e pa r a l l e l p o r t o u t p u t s e c t i o n . <13>: p o r t b , a g c 5 ena b le b i t. w h en this b i t is s e t, a g c 5 da t a ( i / q d a t a ) i s output on p a r a l l el output p o r t a ( d a t a bu s ) . w h e n this b i t is c l ea r e d , a g c 5 da ta do es n o t a p p e a r o n o u t p u t p o r t c.
AD6636 rev. 0 | page 68 of 72 <12>: port b, agc 4 enable bit. similar to bit <13> for agc 4. <11>: port b, agc 3 enable bit. similar to bit <13> for agc 3. <10>: port b, agc 2 enable bit. similar to bit <13> for agc 2. <9>: port b, agc 1 enable bit. similar to bit <13> for r agc 1. <8>: port b, agc 0 enable bit. similar to bit <13> for agc 0. <7>: port a append rssi bit. when this bit is set, an rssi word is appended to every i/q output sample, irrespective of whether or not the rssi word is updated in the agc. when this bit is cleared, an rssi word is appended to an i/q output sample only when the rssi word is updated. the rssi word is not output for subsequent i/q samples until the next time rssi is updated again in the agc. <6>: port a, data format bit. when this bit is set, the port is configured for 8-bit parallel i/q mode. when this bit is cleared, the port is configured for 16-bit interleaved i/q mode. see the parallel port output section. <5>: port a, agc 5 enable bit. when this bit is set, agc 5 data (i/q data) is output on parallel output port a (data bus). when this bit is cleared, agc 5 data does not appear on output port c. <4>: port a, agc 4 enable bit. similar to bit <5> for agc 4. <3>: port a, agc 3 enable bit. similar to bit <5> for agc 3. <2>: port a, agc 2 enable bit. similar to bit <5> for agc 2. <1>: port a, agc 1 enable bit. similar to bit <5> for agc 1. <0>: port a, agc 0 enable bit. similar to bit <5> for agc 0. output port control <9:0> <9:8>: pclk divisor bits. when a parallel port is in master mode, the pclk is derived from the pll_clk. these bits define the value of the divisor used to divide the pll_clk to obtain the pclk. these bits are dont care in slave mode. table 43. pclk divisor bits pclk divisor 7:6 divisor value 00 1 01 2 10 4 11 8 <7>: pclk master mode bit. when the pclk master mode bit is set, the pclk pin is configured as an output and the pclk is driven by the pll_clk. data is transferred out of the AD6636 synchronous to this output clock. when this bit is cleared, the pclk pin is configured as an input. the user is required to provide a pclk, and data is transferred out of the AD6636 synchronous to this input clock. on power-up, this bit is cleared to avoid contention on the pclk pin. <6:4>: complex control bits. these bits are described in table 44. table 44. complex control bits complex control 6:4 comment 000 no complex filters stream control register controls agc usage. 001 str0/1 combined ch 0 and ch 1 form a complex filter. 010 str0/1 combined, str2/3 combined ch 0 and ch 1 form a complex filter; ch 2 and ch 3 form a complex filter. 011 str0/1 combined, str2/3 combined, str 4/5 combined ch 0 and ch 1 form a complex filter; ch 2 and ch 3 form a complex filter; ch 4 and ch 5 form a complex filter. 101 str0/1 combined ch 0 and ch 1 form a biphase filter. 110 str0/1 combined, str2/3 combined ch 0 and ch 1 form a biphase filter; ch 2 and ch 3 to form a biphase filter. 111 str0/1 combined, str2/3 combined, str 4/5 combined ch 0 and ch 1 to form a biphase filter; ch 2 and ch 3 to form a biphase filter; ch 4 and ch 5 to form a biphase filter. <3:0>: stream control bits. these bits are described in table 45. table 45. stream control bits stream control bits output streams (str0, str1, str2, str3, str4, str5) number of streams 0000 ch 0/1 combined; ch 2, ch 3, ch 4, ch 5 independent 5 0001 ch 0/1/2 combined; ch 3, ch 4, ch 5 independent 4 0010 ch 0/1/2/3 combined; ch 4, ch 5 independent 3 0011 ch 0/1/2/3/4 combined; ch 5 independent 2 0100 ch 0/1/2/3/4/5 combined 1 0101 ch 0/1/2 combined, ch 3/4/5 combined 2 0110 ch 0/1 combined, ch 2/3 combined, ch 4/5 combined 3 0111 ch 0/1 combined, ch 2/3 combined, ch 4, ch 5 independent 3 1000 ch 0/1/2 combined, ch 3/4 combined, 5 independent 3 1001 ch 0/1/2/3 combined, ch 4/5 combined. 2 default independent channels 6
AD6636 rev. 0 | page 69 of 72 agc 0, i output <15:0> this read-only register provides the latest in-phase output sample from agc 0. note that agc 0 might be bypassed, and that agc 0 here is representative of the datapath only. agc 0, q output <15:0> this read-only register provides the latest quadrature-phase output sample from agc 0. note that agc 0 might be bypassed, and that agc 0 here is representative of the datapath only. agc 1, i output <15:0> this read-only register provides the latest in-phase output sample from agc 1. note that agc 1 might be bypassed and that agc 1 here is representative of the datapath only. agc 1, q output <15:0> this read-only register provides the latest quadrature-phase output sample from agc 1. note that agc 1 might be bypassed and that agc 1 here is representative of the datapath only. agc 2, i output <15:0: this read-only register provides the latest in-phase output sample from agc 2. note that agc 2 might be bypassed and that agc 2 here is representative of the datapath only. agc 2, q output <15:0> this read-only register provides the latest quadrature-phase output sample from agc 2. note that agc 2 might be bypassed and that agc 2 here is representative of the datapath only. agc 3, i output <15:0> this read-only register provides the latest in-phase output sample from agc 3. note that agc 3 might be bypassed and that agc 3 here is representative of the datapath only. agc 3, q output <15:0> this read-only register provides the latest quadrature-phase output sample from agc 3. note that agc 3 might be bypassed and that agc 3 here is representative of the datapath only. agc 4, i output <15:0> this read-only register provides the latest in-phase output sample from agc 4. note that agc 4 might be bypassed and that agc 4 here is representative of the datapath only. agc 4, q output <15:0> this read-only register provides the latest quadrature-phase output sample from agc 4. note that agc 4 might be bypassed and that agc 4 here is representative of the datapath only. agc 5, i output <15:0> this read-only register provides the latest in-phase output sample from agc 5. note that agc 5 might be bypassed and that agc 5 here is representative of the datapath only. agc 5, q output <15:0> this read-only register provides the latest quadrature-phase output sample from agc 5. note that agc 5 might be bypassed and that agc 5 here is representative of the datapath only. agc 0, rssi output <11:0> this read-only register provides the latest rssi output sample from agc 0. this register is updated only when agc 0 is enabled and operating. agc 1, rssi output <11:0> this read-only register provides the latest rssi output sample from agc 1. this register is updated only when agc 1 is enabled and operating. agc 2, rssi output <11:0> this read-only register provides the latest rssi output sample from agc 2. this register is updated only when agc 2 is enabled and operating. agc 3, rssi output <11:0> this read-only register provides the latest rssi output sample from agc 3. this register is updated only when agc 3 is enabled and operating. agc 4, rssi output <11:0> this read-only register provides the latest rssi output sample from agc 4. this register is updated only when agc 4 is enabled and operating. agc 5, rssi output <11:0> this read-only register provides the latest rssi output sample from agc 5. this register is updated only when agc 5 is enabled and operating.
AD6636 rev. 0 | page 70 of 72 design notes the fol l o w in g g u ide l i n es des c r i b e cir c ui t co n n e c t i o n s, la yo u t r e q u ir em en ts, and p r og ra mming p r o c ed ur es f o r th e AD6636. the desig n er sho u ld r e vi e w t h e s e guide l i n es b e fo r e s t a r t i n g t h e sy stem desig n and l a yo u t . ? the AD6636 r e q u ir es th e f o l l o w in g p o w e r - u p s e q u en ce: th e vd d c o r e (1. 8 v) m u s t s e t t le in t o n o minal vol t a g e leve ls b e fo r e t h e vd di o a t t a in s t h e mini m u m. this en s u r e s t h a t , o n p o w e r - u p , t h e jt a g do es n o t t a k e con t r o l o f t h e i/ o pi ns . ? i n p u t c l o c k s ( c l k a , c l k b , c l k c , c l k d ) a n d i n p u t p o r t p i n s (in a [15:0] t o ind[15:0], exp a [2:0] t o exp d [2:0]) a r e n o t 5 v t o lera n t . c a r e s h o u ld b e t a k e n t o dr i v e t h es e p i n s wi t h in t h e limi t s o f vd d i o (3.0 v t o 3.6 v). ? w h e n t h e a d c output h a s l e ss t h an 1 6 bit s of re s o lut i on , i t s h o u ld be co nn ect e d t o th e ms b s o f th e in p u t po r t (m s b - j u st if ie d). th e rema ini n g ls bs sh o u ld b e co n n e c t e d t o g r ou nd. ? the n u m b er f o r m a t us e d in this p a r t is tw os co m p lem e n t . a l l in p u t p o r t s a nd o u t p u t p o r t s us e tw o s co m p lem e n t da t a fo r m a t . the fo r m a t s fo r i n divi dua l in ter n a l r e g i sters ar e g i v e n i n t h e m e m o r y ma p des c r i p t io n o f t h es e r e g i s t ers. ? i n b o t h m i c r op or t and s e r i a l p o r t op e r a t i o n , t h e dt a c k (rd y , s d o) p i n is a n o p en-dra in o u t p u t and , ther ef o r e , s h o u ld b e p u l l ed hig h ext e r n al l y usin g a p u l l -u p r e sis t er . the r e co mm e nde d val u e fo r t h e p u l l -u p r e sis t or is f r o m 1 k? a nd 5 k?. 04998-0-050 dtack (rdy, sdo) AD6636 1k ? 3.3v f i g u re 50. dt a c k , sdo p u ll-up resist or c i rcuit ? a sim p le rc cir c ui t is us ed o n t h e e x t_fil t e r p i n t o b a lan c e t h e in t e r n a l r c cir c ui t o n t h is p i n and ma in t a i n a g ood p l l c l oc k l o c k . t h e r e c o m m en d e d c i r c u i t i s s h o w n in f i g u re 5 1 , w i t h t h e r c c i rc u i t c o n n e c te d to v d d c or e . this r c cir c ui t s h o u ld b e p l ace d as c l os e as p o ssi b l e t o t h e AD6636 p a r t . this la yo u t en s u r e s tha t t h e p l l c l o c k is v o id o f n o is e and spurs a n d t h e pll lo ck is ma i n t a i n e d clo s ely . 04998-0-051 ext_filter AD6636 10k ? v ddcore (1.8v) 0.01 f f i gur e 5 1 . ex t_ fil t er ci r c ui t for p l l clo c k ? by defa u l t, t h e pll cl k is dis a b l e d . i t can b e e n a b le d b y p r og ra mmin g t h e pll m u lt i p li er a nd divider b i ts i n t h e ad c cl k con t r o l r e g i s t er . w h en t h e p ll clk is ena b le d b y p r og ra mmin g this r e g i s t er , i t tak e s abo u t 50 t o 200 s t o s e t t le down. w h i l e t h e p ll lo o p s e t t les do w n , t h e v o l t a g e a t th e ex t _ f i l t er p i n in c r ea se s f r o m 0 v t o v d d c o r e ( 1 . 8 v) a nd s e t t les t h er e. c h a n nel reg i sters and o u tp u t p o r t r e g i s t ers (a ddr es s e s 0x68 t o 0xe7) s h o u ld n o t b e p r o- g r a m m e d bef o r e th e p ll lo o p s e t t les do wn. ? the l v ds_ r s e t p i n is us e d t o calib r a t e t h e c u r r en t i n t h e l v ds p a ds. t h e r e co mm e nde d cir c ui t fo r t h is p i n is sh o w n in f i gur e 52. this r e sis t o r s h o u l d b e p l ac ed as c l os e as p o s s i b le t o t h e AD6636 p a r t . this r e sis t o r is n o t r e q u ir ed , if cm os m o de in p u t is us ed . 04998-0-052 lvds_rset AD6636 10k ? f i gure 52. l v ds _r s e t circuit f o r l v ds cal i br atio n ? t o r e s e t t h e AD6636 p a r t , th e us er n e e d s t o p r o v ide a mini m u m p u ls e o f 30 n s to t h e res e t pi n . t h e res e t pi n shou l d b e c o n n e c te d to g n d ( o r pu l l e d l o w) d u r i ng p o we r - u p o f t h e p a r t . the res e t p i n can b e p u l l e d hig h a f te r t h e p o w e r su p p lies ha ve s e t t le d to n o m i na l va l u es ( 1 .8 v a nd 3.3 v). a t this p o in t, a p u ls e (p u l l lo w an d hig h a g a i n) sh o u ld be prov i d e d to g i ve a res e t to t h e p a r t . ? m o s t AD6636 p i n s a r e dr i v en b y bo th j t a g circ ui tr y a n d n o r m al f u n c tio n cir c ui tr y s p ecif ic t o eac h p i n. trst is t h e re s e t pi n f o r j t a g . w h e n trst is p u l l e d lo w , jt a g is in r e s e t a nd a l l p i ns f u n c t i on in n o r m a l m o de ( d r i ven b y fu n c ti o n al ci r c ui t ) . i f j t a g i s n o t u s ed in th e de s i gn , th e trst p i n sh o u ld be p u l l ed lo w a t al l t i m e s.
AD6636 rev. 0 | page 71 of 72 if jtag is used, the designer should ensure that the trst pin is pulled low during power-up. after the power supplies have settled to nominal values (1.8 v and 3.3 v), the trst pin can be pulled high for jtag control. when jtag control is no longer required, the trst pin should ideally be pulled low again. ? the cpuclk (sclk) is the clock used for programming via the microport (serial port). this clock needs to be provided by the designer to the part (slave clock). the designer should ensure that this clocks frequency is less than or equal to the frequency of the clka signal. additionally, the frequency of the cpuclk (sclk) should always be less than 100 mhz. ? clka, clkb, clkc, and clkd are used as individual clocks to input data into input ports a, b, c, and d, respectively. all these clocks are required to have same frequency and should ideally be generated from the same clock source. note that clka is used to drive the internal circuitry and the pll clock multiplier. therefore, even if input port a is not used, clka should be driven by the input clock. ? the microport data bus is 16 bits wide. both 8-bit and 16 bit modes are available using this part. if 8-bit mode is used, the msb of the data bus (d[15:8]) can be left floating or connected to gnd. ? the output parallel port has a one clock cycle overhead. if two channels (with the same data rates) are output on one output port in 16-bit interleaved i/q mode along with an agc word, this requires three clock cycles for one sample from each channel (one clock each for i data, q data, and gain data). therefore, the total number of clock cycles required to output the data is 3 clocks/channel 2 channels + 1 (overhead) = 7 clock cycles. the number of clock cycles required for each channel can be 3 (interleaved i + q + gain word), or 2 (parallel i /q + gain) or 2 (interleaved i + q) or 1 (interleaved i/q). designers should make sure that sufficient time is allowed to output these channels on one output port. also note that the i, q, and gain for a particular channel all come out on a single output port and cannot be divided among output ports. ? when crcf and drcf filters are disabled, the coefficient memory cannot be read back, because the clock to the coefficient ram is also cut off. ? in the intel mode microport, the beginning of a read and write access is indicated by the rdy pin going low. the access is complete only when the rdy pin goes high. in the motorola mode microport, the completion of a read and write access is indicated by the dtack going low. in both modes, cs , rd ( ds ), and wr (r/ w ) should be active until access is complete; otherwise, an incomplete access results. ? in both intel and motorola modes, if cs is held low even after microport read or write access is complete, the microport initiates a second access. this is a problem while writing or reading from coefficient ram, where each access writes to or reads from a different ram address. this can be fixed by writing to one coefficient ram address at a time, that is, the coefficient start and stop address registers have the same value. ? in spi mode programming, the scs pin needs to go high (inactive) after writing or reading each byte (eight clock cycles on the sclk pin).
AD6636 rev. 0 | page 72 of 72 outline dimensions 1.00 bsc a b c d e f g h j k l m n p r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 bottom view 15.00 bsc sq a1 corner index area 16 t seating plane 1.31* 1.21 1.10 coplanarity 0.20 0.70 0.60 0.50 ball diameter 0.30 min* detail a top view detail a 1.85* 1.71 1.40 17.20 17.00 sq 16.80 ball a1 corner compliant to jedec standards mo-192-aaf-1 except for dimensions indicated by a "*" symbol. f i g u re 53. 2 56-l e a d chip s c al e b a l l gr id a r r a y [csp _bg a ] (bc-25 6-2) di me nsio ns sho w n i n mi ll im e t e r s ordering guide model temperature r a nge package descri ption package option AD6636bbcz 1 ?40c to +85c 6-channe l part, 256-lead csp_bga bc-256-2 AD6636cbcz 1 ?40c to +85c 4-channe l part, 256-lead csp_bga bc-256-2 AD6636bc/pcb evaluation boar d with AD6636 (6 -channe l part) and software pcb assem b led 1 z = pb-free part. ? 2004 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . d04998C0C 8/04(0)

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